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MC10134FN PDF预览

MC10134FN

更新时间: 2024-11-11 22:54:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 复用器触发器锁存器逻辑集成电路
页数 文件大小 规格书
5页 108K
描述
Dual Multiplexer With Latch

MC10134FN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCJ, LDCC20,.4SQ
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.8
Is Samacsys:N其他特性:2:1 MUX FOLLOWED BY LATCH; WITH ADDITIONAL COMMON LATCH ENABLE
系列:10KJESD-30 代码:S-PQCC-J20
JESD-609代码:e0长度:8.965 mm
逻辑集成电路类型:D LATCH位数:1
功能数量:2输入次数:2
端子数量:20最高工作温度:85 °C
最低工作温度:-30 °C输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:-5.2 V
最大电源电流(ICC):60 mAProp。Delay @ Nom-Sup:6.3 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Multiplexer/Demultiplexers表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:LOW LEVEL
宽度:8.965 mmBase Number Matches:1

MC10134FN 数据手册

 浏览型号MC10134FN的Datasheet PDF文件第2页浏览型号MC10134FN的Datasheet PDF文件第3页浏览型号MC10134FN的Datasheet PDF文件第4页浏览型号MC10134FN的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10134 is a dual multiplexer with clocked D type latches. Each latch  
may be clocked separately by holding the common clock in the low state, and  
using the clock enable inputs for the clocking function. If the common clock is to  
be used to clock the latch, the clock enable (CE) inputs must be in the low state.  
In this mode, the enable inputs perform the function of controlling the common  
clock (C ).  
C
The data select inputs determine which data input is enabled. A high (H)  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
level on the A0 input enables data input D12 and a low (L) level on the A0 input  
enables data input D11. A high (H) level on the A1 input enables data input D22  
and a low (L) level on the A1 input enables data input D21.  
Any change on the data input will be reflected at the outputs while the clock is  
low. The outputs are latched on the positive transition of the clock. While the  
clock is in the high state, a change in the information present at the data inputs  
will not affect the output information.  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
FN SUFFIX  
PLCC  
CASE 775–02  
P
= 225 mW typ/pkg (No Load)  
= 3.0 ns typ  
D
t
pd  
t , t = 2.5 ns typ (20%–80%)  
r f  
DIP  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
A0  
6
Q1  
Q2  
A1 11  
Q1  
D11  
D12  
A0  
Q2  
D11  
4
2
3
Q1  
Q1  
D21  
D22  
A1  
D12  
CEO 10  
5
C
7
C
C
C
CEO  
CE1  
15 Q2  
CE1  
9
D21 13  
D22 12  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
14 Q2  
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
TRUTH TABLE  
C
L
L
L
L
H
A0 D11 D12  
Q
n+1  
L
L
L
L
H
X
X
X
X
X
L
H
L
H
H
X
H
X
H
Q
n
C = C + C  
E
C
3/93  
Motorola, Inc. 1996  
REV 5  

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