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MC10186L PDF预览

MC10186L

更新时间: 2024-11-04 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
8页 111K
描述
Hex D Master-Slave Flip-Flop with Reset

MC10186L 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:CERAMIC, DIP-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.21
Is Samacsys:N其他特性:COMMON RESET, RESET ACTIVE ONLY WHEN CLOCK IS LOW
系列:10KJESD-30 代码:R-CDIP-T16
JESD-609代码:e0长度:19.495 mm
逻辑集成电路类型:D FLIP-FLOP位数:1
功能数量:6端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
输出特性:OPEN-EMITTER输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE最大电源电流(ICC):121 mA
传播延迟(tpd):4.5 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
表面贴装:NO技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:125 MHz
Base Number Matches:1

MC10186L 数据手册

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MC10186  
Hex D Master-Slave  
Flip-Flop with Reset  
The MC10186 contains six high–speed, master slave type “D”  
flip–flops. Clocking is common to all six flip–flops. Data is entered  
into the master when the clock is low. Master to slave data transfer  
takes place on the positive–going Clock transition. Thus, outputs may  
change only on a positive–going Clock transition. A change in the  
information present at the data (D) input will not affect the output  
information any other time due to the master–slave construction of this  
device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT.  
RESET ONLY FUNCTIONS WHEN CLOCK IS LOW.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10186L  
AWLYYWW  
P = 460 mW typ/pkg (No Load)  
D
1
f  
= 150 MHz (typ)  
toggle  
16  
t , t = 2.0 ns typ (20%–80%)  
r
f
PDIP–16  
P SUFFIX  
CASE 648  
MC10186P  
AWLYYWW  
LOGIC DIAGRAM  
1
1
D0  
D1  
5
6
2
Q0  
Q1  
PLCC–20  
FN SUFFIX  
CASE 775  
10186  
AWLYYWW  
3
4
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
D2  
7
Q2  
WW = Work Week  
DIP PIN ASSIGNMENT  
D3 10  
D4 11  
D5 12  
13 Q3  
14 Q4  
15 Q5  
RESET  
Q0  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Q5  
Q4  
Q1  
Q3  
Q2  
D5  
D0  
D4  
D1  
CLOCK 9  
RESET 1  
D3  
D2  
V
CC  
= PIN 16  
= PIN 8  
V
EE  
CLOCK  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables  
on page 18 of the ON Semiconductor MECL Data Book  
(DL122/D).  
CLOCKED TRUTH TABLE  
R
L
C
L
D
X
L
Qn + 1  
Q
n
L
H*  
H*  
L
L
H
L
ORDERING INFORMATION  
L
H
X
Device  
Package  
Shipping  
H
MC10186L  
CDIP–16  
25 Units / Rail  
*A clock H is a clock transition  
from a low to a high state.  
MC10186P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
MC10186FN  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10186/D  

MC10186L 替代型号

型号 品牌 替代类型 描述 数据表
MC10135L ONSEMI

完全替代

Dual J-K Master-Slave Flip-Flop
MC10H186FNG ONSEMI

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Hex D Master−Slave Flip−Flop with Reset
MC10H131FNG ONSEMI

功能相似

Dual D Type Master−Slave Flip−Flop

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