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M74HC7294C1 PDF预览

M74HC7294C1

更新时间: 2024-09-19 12:59:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 预分频器多谐振动器逻辑集成电路时钟
页数 文件大小 规格书
14页 301K
描述
HC/UH SERIES, PRESCALER, PQCC20, PLASTIC, LCC-20

M74HC7294C1 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N系列:HC/UH
JESD-30 代码:S-PQCC-J20JESD-609代码:e0
长度:8.9662 mm逻辑集成电路类型:PRESCALER
最大频率@ Nom-Sup:26000000 Hz数据/时钟输入次数:2
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):571 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Prescaler/Multivibrators
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.9662 mm最小 fmax:31 MHz
Base Number Matches:1

M74HC7294C1 数据手册

 浏览型号M74HC7294C1的Datasheet PDF文件第2页浏览型号M74HC7294C1的Datasheet PDF文件第3页浏览型号M74HC7294C1的Datasheet PDF文件第4页浏览型号M74HC7294C1的Datasheet PDF文件第5页浏览型号M74HC7294C1的Datasheet PDF文件第6页浏览型号M74HC7294C1的Datasheet PDF文件第7页 
M54/74HC292/7292  
M54/74HC294/7294  
PROGRAMMABLE DIVIDER/TIMER  
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HIGH SPEED  
MAX = 70 MHz (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 mA (MAX.) at TA = 25 oC  
HIGH NOISE IMMUNITY  
f
V
NIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
| IOH|= IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS292/294  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXB1R  
M74HCXXXM1R  
M74HCXXXC1R  
DESCRIPTION  
The 54/74HC292/7292 and HC294/7294 are high  
speed CMOS PROGRAMMABLE DIVIDER/TIMER  
fabricated with silicon C2MOS technology.  
types feature an active-low clear input to initialize  
the state of all flip-flops. To facilitate incoming  
inspection, test points are provided. (TP1, TP2 and  
TP3 on the HC292/7292 and TP on the  
HC294/7294). All inputs are equipped with  
protection circuits against static discharge and  
transient excess voltage.  
They achieve the high speed operation similar to  
equivalent LSTTL while maintaining the CMOS low  
power dissipation.  
These devices are programmable frequency  
dividers. The typeshave two clockinputs, either one  
may be used for clock gating. (see the function  
table). The HC292/7292 can divide from 22 to 231,  
and the HC294/7294 can divide from 22 to 215. The  
HC292/294 have Q output with ”Totem pole”  
configuration and test point TP with ”Open Drain”  
output configuration.  
HC7292/7294 have all outputs ”Totem Pole.  
PIN CONNECTION (top view)  
HC292  
HC7292  
HC294  
HC7294  
HC292  
HC7292  
HC294  
HC7294  
October 1993  
1/14  

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