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M74HC74 PDF预览

M74HC74

更新时间: 2024-11-01 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
11页 252K
描述
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR

M74HC74 数据手册

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M54HC74  
M74HC74  
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR  
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HIGH SPEED  
fMAX = 71 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 2 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS74  
ORDER CODES :  
M54HC74F1R  
M74HC74B1R  
M74HC74M1R  
M74HC74C1R  
DESCRIPTION  
PIN CONNECTIONS (top view)  
The M54/74HC74 is a high speed CMOS DUAL D  
TYPE FLOP WITH PRESET AND CLEAR fabri-  
cated in silicon gate C2MOS technology. It has the  
same high speed performance of LSTTL combined  
with trueCMOSlow power consumption. A signal on  
the DINPUT is transferred to the Q OUTPUTduring  
the positive going transition of the clock pulse.  
CLEAR and PRESET are independent of the clock  
and accomplished by alow on the appropriate input.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
October 1992  
1/11  

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