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M74HC76 PDF预览

M74HC76

更新时间: 2024-11-01 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
11页 254K
描述
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC76 数据手册

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M54HC76  
M74HC76  
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
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HIGH SPEED  
fMAX = 65 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 2 µA (MAX.) AT 25 °C  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
tPLH = tPHL  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS76  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HC76F1R  
M74HC76B1R  
M74HC76M1R  
M74HC76C1R  
DESCRIPTION  
The M54/74HC76 is a high speed CMOSDUAL J-K  
FLIP FLOP fabricated in silicon gate C2MOS tech-  
nology. It has the same high speed performance of  
LSTTL combined with true CMOS low power con-  
sumption. Depending on with the logic level at the J  
and K inputs this device changes state on thenega-  
tive going transition of the clock pulse. CLEAR and  
PRESET are independent of the clock and are ac-  
complished by a logic low on the corresponding  
input. All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
PIN CONNECTIONS (top view)  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
October 1992  
1/11  

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