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M74HC76RM13TR PDF预览

M74HC76RM13TR

更新时间: 2024-09-18 22:22:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
11页 511K
描述
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC76RM13TR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.82
其他特性:MASTER SLAVE OPERATION系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:21000000 Hz
最大I(ol):0.004 A位数:2
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):190 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:3.9 mm
最小 fmax:25 MHzBase Number Matches:1

M74HC76RM13TR 数据手册

 浏览型号M74HC76RM13TR的Datasheet PDF文件第2页浏览型号M74HC76RM13TR的Datasheet PDF文件第3页浏览型号M74HC76RM13TR的Datasheet PDF文件第4页浏览型号M74HC76RM13TR的Datasheet PDF文件第5页浏览型号M74HC76RM13TR的Datasheet PDF文件第6页浏览型号M74HC76RM13TR的Datasheet PDF文件第7页 
M74HC76  
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED :  
= 67MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC76B1R  
M74HC76M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 76  
M74HC76RM13TR  
M74HC76TTR  
TSSOP  
DESCRIPTION  
The M74HC76 is an high speed CMOS DUAL J-K  
FLIP FLOP WITH CLEAR fabricated with silicon  
gate C MOS technology.  
and PRESET (PR) are independent of the clock  
and are accomplished by a logic low on the  
corresponding input.  
2
Depending on with the logic level at J and K  
inputs, this device changes state on the negative  
going transition of clock pulse (CK). CLEAR (CLR)  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

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