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M74HC77M1 PDF预览

M74HC77M1

更新时间: 2024-09-19 13:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 244K
描述
HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO14, MICRO, GULLWIING, PLASTIC, DIP-14

M74HC77M1 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:MICRO, GULLWIING, PLASTIC, DIP-14
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.89
Is Samacsys:N系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:D LATCH最大I(ol):0.004 A
位数:2功能数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:36 ns
传播延迟(tpd):36 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:HIGH LEVEL
宽度:3.9 mmBase Number Matches:1

M74HC77M1 数据手册

 浏览型号M74HC77M1的Datasheet PDF文件第2页浏览型号M74HC77M1的Datasheet PDF文件第3页浏览型号M74HC77M1的Datasheet PDF文件第4页浏览型号M74HC77M1的Datasheet PDF文件第5页浏览型号M74HC77M1的Datasheet PDF文件第6页浏览型号M74HC77M1的Datasheet PDF文件第7页 
M54HC77  
M74HC77  
4-BIT D-TYPE LATCH  
.
.
.
.
.
.
.
.
HIGH SPEED  
tPD = 10 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 2 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS77  
ORDER CODES :  
M54HC77F1R  
M74HC77B1R  
M74HC77M1R  
M74HC77C1R  
DESCRIPTION  
The M54/74HC77 is a high speed CMOS 4-BIT D-  
TYPE LATCH fabricated in silicon gate C2MOS tech-  
nology. It has the same high speed performance of  
LSTTL combined with true CMOS low power con-  
sumption. It contains two groups of 2-bit latches con-  
trolled by an enable input (G1 2 or G3 4). These  
two latch groups can be used in different circuits. The  
data applied to the data inputs (1D, 2D, or 3D, 4D) are  
transfered to the Q outputs (1Q, 2Q, or 3Q, 4Q) re-  
spectively when the enable input (G1 2 or G3 4) is  
taken high. The Q outputs will follow the data inputs  
as long asthe enable input is kept high. When the en-  
able input istaken low, theinformation data applied to  
the data inputs is retained at the Q outputs. All inputs  
areequipped with protection circuits against staticdis-  
charge and transient excess voltage.  
PIN CONNECTIONS (top view)  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
October 1992  
1/10  

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