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M74HC77RM13TR PDF预览

M74HC77RM13TR

更新时间: 2024-11-01 22:22:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器
页数 文件大小 规格书
10页 255K
描述
4 BIT D TYPE LATCH

M74HC77RM13TR 数据手册

 浏览型号M74HC77RM13TR的Datasheet PDF文件第2页浏览型号M74HC77RM13TR的Datasheet PDF文件第3页浏览型号M74HC77RM13TR的Datasheet PDF文件第4页浏览型号M74HC77RM13TR的Datasheet PDF文件第5页浏览型号M74HC77RM13TR的Datasheet PDF文件第6页浏览型号M74HC77RM13TR的Datasheet PDF文件第7页 
M74HC77  
4 BIT D TYPE LATCH  
HIGH SPEED :  
= 11 ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC77B1R  
M74HC77M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 77  
M74HC77RM13TR  
M74HC77TTR  
TSSOP  
DESCRIPTION  
The M74HC77 is an high speed CMOS 4 BIT D  
TYPE LATCH fabricated with silicon gate C MOS  
technology.  
It contains two groups of 2 bit latches controlled by  
an enable input (G12 or G34). These two latch  
groups can be used in different circuits. The data  
applied to the data inputs (1D, 2D, or 3D, 4D) are  
transferred to the Q outputs (1Q, 2Q, or 3Q, 4Q)  
respectively when the enable input (G12 or G34)  
is taken high. The Q outputs will follow the data  
inputs as long as the enable input is kept high.  
When the enable input is taken low, the  
information data applied to the data input is  
retained at the Q outputs.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/10  

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