M74HC77RM13TR

更新时间： 2024-11-07 22:22:19

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		锁存器
页数	文件大小	规格书
10页	255K
描述
4 BIT D TYPE LATCH

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中文翻译

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数据手册

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M74HC77RM13TR 数据手册

M74HC77

4 BIT D TYPE LATCH

■

HIGH SPEED :

= 11 ns (TYP.) at V = 6V

LOW POWER DISSIPATION:

=2µA(MAX.) at T =25°C

HIGH NOISE IMMUNITY:

= V = 28 % V (MIN.)

NIH

NIL

DIP

SOP

TSSOP

T & R

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 4mA (MIN)

BALANCED PROPAGATION DELAYS:

ORDER CODES

PACKAGE

PLH

PHL

WIDE OPERATING VOLTAGE RANGE:

(OPR) = 2V to 6V

TUBE

DIP

SOP

M74HC77B1R

M74HC77M1R

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 77

M74HC77RM13TR

M74HC77TTR

TSSOP

DESCRIPTION

The M74HC77 is an high speed CMOS 4 BIT D

TYPE LATCH fabricated with silicon gate C MOS

technology.

It contains two groups of 2 bit latches controlled by

an enable input (G1•2 or G3•4). These two latch

groups can be used in different circuits. The data

applied to the data inputs (1D, 2D, or 3D, 4D) are

transferred to the Q outputs (1Q, 2Q, or 3Q, 4Q)

respectively when the enable input (G1•2 or G3•4)

is taken high. The Q outputs will follow the data

inputs as long as the enable input is kept high.

When the enable input is taken low, the

information data applied to the data input is

retained at the Q outputs.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

1/10

12 3 4 5 6 7...10

中文翻译

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与M74HC77RM13TR相关器件

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