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M74HC76-1 PDF预览

M74HC76-1

更新时间: 2024-11-01 22:28:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
11页 511K
描述
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC76-1 数据手册

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M74HC76  
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED :  
= 67MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC76B1R  
M74HC76M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 76  
M74HC76RM13TR  
M74HC76TTR  
TSSOP  
DESCRIPTION  
The M74HC76 is an high speed CMOS DUAL J-K  
FLIP FLOP WITH CLEAR fabricated with silicon  
gate C MOS technology.  
and PRESET (PR) are independent of the clock  
and are accomplished by a logic low on the  
corresponding input.  
2
Depending on with the logic level at J and K  
inputs, this device changes state on the negative  
going transition of clock pulse (CK). CLEAR (CLR)  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

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