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M74HC7645M1R PDF预览

M74HC7645M1R

更新时间: 2024-11-01 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器
页数 文件大小 规格书
10页 259K
描述
OCTAL BUS TRANSCEIVER (3-STATE):HC7645 NONINVERTING HC7640 INVERTING ,HC7643 INVERTING/NONINVERTING

M74HC7645M1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84其他特性:WITH DIRECTION CONTROL
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:HC/UHJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:38 ns
传播延迟(tpd):190 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:7.5 mmBase Number Matches:1

M74HC7645M1R 数据手册

 浏览型号M74HC7645M1R的Datasheet PDF文件第2页浏览型号M74HC7645M1R的Datasheet PDF文件第3页浏览型号M74HC7645M1R的Datasheet PDF文件第4页浏览型号M74HC7645M1R的Datasheet PDF文件第5页浏览型号M74HC7645M1R的Datasheet PDF文件第6页浏览型号M74HC7645M1R的Datasheet PDF文件第7页 
M54HC7245/7640/7643/7645  
M74HC7245/7640/7643/7645  
OCTAL BUS TRANSCEIVER (3-STATE): HC7645 NON INVERTING  
HC7640 INVERTING , HC7643 INVERTING/NON INVERTING  
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HIGH SPEED  
t
PD = 12 ns (TYP.) at VCC = 5V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 oC  
HIGH NOISE IMMUNITY  
VH = 1.1 (TYP.) at VCC = 5V  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING RANGE  
VCC (OPR) = 2V to 6V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS245/640/643  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HCXXXXF1R  
M74HCXXXXB1R  
M74HCXXXXM1R  
M74HCXXXXC1R  
DESCRIPTION  
TheM54/74HC7245 HC7640, HC7643 and HC7645  
utilise silicon gate C2MOS technology to achive  
operating speeds equivalent to LSTTL devices.  
Along with the low power dissipation and high noise  
immunity of standads C2MOS integrated circuit, it  
possesses the capability to drive 15 LSTTL loads.  
These IC’s are intended for two-way asynchronous  
communication between data buses, and the  
direction of data trasmission is determined by DIR  
input. Theenableinput(G)canbeused todisable the  
device so that the buses are effectively isolated.  
The HC7245/640/7643/7645 have the same pin  
configuration and function as the HC245/640/643  
and they have a hysteresis characteristics with each  
input, so HC7245/7640/7643/7645 can be used as a  
line receiver, etc. All input are equipped with  
protection circuits against static discharge and  
transient excess voltage.  
IT IS PROHIBITEDTOAPPLY A SIGNAL TOA BUS  
TERMINAL WHEN IT IS IN OUTPUT MODE AND  
WHEN A BUS THERMINAL IS FLOATING (HIGH  
IMPEDANCE STATE), IT IS REQUESTED TO FIX  
THE INPUT LEVEL BY MEANS OF EXTERNAL  
PULL DOWN OR PULL UP RESISTOR.  
PIN CONNECTION (top view)  
HC7640  
HC7643  
HC7645/HC7245  
HC7245 is electrically and funcutionally the same as the HC7645  
January 1994  
1/10  

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