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M74HC75B1R PDF预览

M74HC75B1R

更新时间: 2024-11-07 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器
页数 文件大小 规格书
10页 271K
描述
4 BIT D TYPE LATCH

M74HC75B1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.57
系列:HC/UHJESD-30 代码:R-PDIP-T16
JESD-609代码:e3负载电容(CL):50 pF
逻辑集成电路类型:D LATCH最大I(ol):0.004 A
位数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:33 ns传播延迟(tpd):190 ns
认证状态:Not Qualified座面最大高度:5.1 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:HIGH LEVEL宽度:7.62 mm
Base Number Matches:1

M74HC75B1R 数据手册

 浏览型号M74HC75B1R的Datasheet PDF文件第2页浏览型号M74HC75B1R的Datasheet PDF文件第3页浏览型号M74HC75B1R的Datasheet PDF文件第4页浏览型号M74HC75B1R的Datasheet PDF文件第5页浏览型号M74HC75B1R的Datasheet PDF文件第6页浏览型号M74HC75B1R的Datasheet PDF文件第7页 
M74HC75  
4 BIT D TYPE LATCH  
HIGH SPEED :  
= 11ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC75B1R  
M74HC75M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 75  
M74HC75RM13TR  
M74HC75TTR  
TSSOP  
DESCRIPTION  
The M74HC75 is an high speed CMOS 4 BIT D  
TYPE LATCH fabricated with silicon gate C MOS  
technology.  
It contains two groups of 2 bit latches controlled by  
an enable input (G12 or G34). These two latch  
groups can be used in different circuits. Each latch  
has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The  
data applied to the data input is transferred to the  
Q and Q outputs when the enable input is taken  
high and the outputs will follow the data input as  
long as the enable input is kept high. When the  
enable input is taken low, the information data  
applied to the data input is retained at the outputs.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/10  

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