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M74HC75-1 PDF预览

M74HC75-1

更新时间: 2024-11-01 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器
页数 文件大小 规格书
10页 271K
描述
4 BIT D TYPE LATCH

M74HC75-1 数据手册

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M74HC75  
4 BIT D TYPE LATCH  
HIGH SPEED :  
= 11ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC75B1R  
M74HC75M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 75  
M74HC75RM13TR  
M74HC75TTR  
TSSOP  
DESCRIPTION  
The M74HC75 is an high speed CMOS 4 BIT D  
TYPE LATCH fabricated with silicon gate C MOS  
technology.  
It contains two groups of 2 bit latches controlled by  
an enable input (G12 or G34). These two latch  
groups can be used in different circuits. Each latch  
has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The  
data applied to the data input is transferred to the  
Q and Q outputs when the enable input is taken  
high and the outputs will follow the data input as  
long as the enable input is kept high. When the  
enable input is taken low, the information data  
applied to the data input is retained at the outputs.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/10  

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