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M74HC74TTR PDF预览

M74HC74TTR

更新时间: 2024-09-18 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 456K
描述
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR

M74HC74TTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:16 weeks风险等级:5.27
系列:HC/UHJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:21000000 Hz最大I(ol):0.004 A
湿度敏感等级:3位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):225 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:25 MHzBase Number Matches:1

M74HC74TTR 数据手册

 浏览型号M74HC74TTR的Datasheet PDF文件第2页浏览型号M74HC74TTR的Datasheet PDF文件第3页浏览型号M74HC74TTR的Datasheet PDF文件第4页浏览型号M74HC74TTR的Datasheet PDF文件第5页浏览型号M74HC74TTR的Datasheet PDF文件第6页浏览型号M74HC74TTR的Datasheet PDF文件第7页 
M74HC74  
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED :  
= 67MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC74B1R  
M74HC74M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 74  
M74HC74RM13TR  
M74HC74TTR  
TSSOP  
DESCRIPTION  
The M74HC74 is an high speed CMOS DUAL D  
TYPE FLIP FLOP WITH CLEAR fabricated with  
silicon gate C MOS technology.  
A signal on the D INPUT is transferred on the Q  
OUTPUT during the positive going transition of the  
clock pulse. CLEAR and PRESET are  
independent of the clock and accomplished by a  
low on the appropriate input.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/12  

M74HC74TTR 替代型号

型号 品牌 替代类型 描述 数据表
MC74HC74ADTR2G ONSEMI

功能相似

Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
SN74HC74PWR TI

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DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
MM74HC74AMTCX FAIRCHILD

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Dual D-Type Flip-Flop with Preset and Clear

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