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MM74HC74AMTCX PDF预览

MM74HC74AMTCX

更新时间: 2024-11-15 22:49:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
8页 93K
描述
Dual D-Type Flip-Flop with Preset and Clear

MM74HC74AMTCX 数据手册

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September 1983  
Revised January 2005  
MM74HC74A  
Dual D-Type Flip-Flop with Preset and Clear  
The 74HC logic family is functionally and pinout compatible  
with the standard 74LS logic family. All inputs are protected  
from damage due to static discharge by internal diode  
clamps to VCC and ground.  
General Description  
The MM74HC74A utilizes advanced silicon-gate CMOS  
technology to achieve operating speeds similar to the  
equivalent LS-TTL part. It possesses the high noise immu-  
nity and low power consumption of standard CMOS inte-  
grated circuits, along with the ability to drive 10 LS-TTL  
loads.  
Features  
Typical propagation delay: 20 ns  
This flip-flop has independent data, preset, clear, and clock  
inputs and Q and Q outputs. The logic level present at the  
data input is transferred to the output during the positive-  
going transition of the clock pulse. Preset and clear are  
independent of the clock and accomplished by a low level  
at the appropriate input.  
Wide power supply range: 2–6V  
Low quiescent current: 40 µA maximum (74HC Series)  
Low input current: 1 µA maximum  
Fanout of 10 LS-TTL loads  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
MM74HC74AM  
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
MM74HC74AMX_NL  
MM74HC74ASJ  
MM74HC74AMTC  
MM74HC74AMTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
MM74HC74AN  
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Connection Diagram  
Truth Table  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Inputs  
Outputs  
PR  
L
CLR  
H
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
L
X
H
L
X
H (Note 1)  
H (Note 1)  
H
H
H
H
H
L
L
H
H
H
L
X
Q0  
Q 0  
Note: Q0 = the level of Q before the indicated input conditions were estab-  
lished.  
Note 1: This configuration is nonstable; that is, it will not persist when pre-  
set and clear inputs return to their inactive (HIGH) level.  
© 2005 Fairchild Semiconductor Corporation  
DS005106  
www.fairchildsemi.com  

MM74HC74AMTCX 替代型号

型号 品牌 替代类型 描述 数据表
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