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M74HC73TTR PDF预览

M74HC73TTR

更新时间: 2024-11-01 22:14:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 326K
描述
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC73TTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:7.83Is Samacsys:N
其他特性:MASTER SLAVE OPERATION系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A位数:2
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):190 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:4.4 mm
最小 fmax:24 MHzBase Number Matches:1

M74HC73TTR 数据手册

 浏览型号M74HC73TTR的Datasheet PDF文件第2页浏览型号M74HC73TTR的Datasheet PDF文件第3页浏览型号M74HC73TTR的Datasheet PDF文件第4页浏览型号M74HC73TTR的Datasheet PDF文件第5页浏览型号M74HC73TTR的Datasheet PDF文件第6页浏览型号M74HC73TTR的Datasheet PDF文件第7页 
M74HC73  
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED :  
= 80MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC73B1R  
M74HC73M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 73  
M74HC73RM13TR  
M74HC73TTR  
TSSOP  
DESCRIPTION  
The M74HC73 is an high speed CMOS DUAL J-K  
FLIP FLOP WITH CLEAR fabricated with silicon  
gate C MOS technology.  
clear function is accomplished independently of  
the clock condition when the clear input (CLR) is  
taken low.  
2
Depending on the logic level applied to J and K  
inputs, this device changes state on the negative  
going transition of clock input pulse (CK). The  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

M74HC73TTR 替代型号

型号 品牌 替代类型 描述 数据表
74ABT74N NXP

类似代替

Dual D-type flip-flop
SN74LS73ADR TI

功能相似

暂无描述
SN74AS74AN TI

功能相似

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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