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M74HC73-1 PDF预览

M74HC73-1

更新时间: 2024-11-07 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
11页 326K
描述
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC73-1 数据手册

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M74HC73  
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED :  
= 80MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC73B1R  
M74HC73M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 73  
M74HC73RM13TR  
M74HC73TTR  
TSSOP  
DESCRIPTION  
The M74HC73 is an high speed CMOS DUAL J-K  
FLIP FLOP WITH CLEAR fabricated with silicon  
gate C MOS technology.  
clear function is accomplished independently of  
the clock condition when the clear input (CLR) is  
taken low.  
2
Depending on the logic level applied to J and K  
inputs, this device changes state on the negative  
going transition of clock input pulse (CK). The  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

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