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KM23V64000BG-12 PDF预览

KM23V64000BG-12

更新时间: 2024-11-25 14:43:03
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
4页 72K
描述
MASK ROM, 4MX16, 120ns, CMOS, PDSO44, 0.600 INCH, SOP-44

KM23V64000BG-12 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
Is Samacsys:N最长访问时间:120 ns
其他特性:CONFIGURABLE AS 4M X 16备用内存宽度:8
JESD-30 代码:R-PDSO-G44长度:28.5 mm
内存密度:67108864 bit内存集成电路类型:MASK ROM
内存宽度:16功能数量:1
端子数量:44字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX16封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:3.1 mm
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:12.6 mm
Base Number Matches:1

KM23V64000BG-12 数据手册

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Advance Information  
KM23V64000BG  
CMOS MASK ROM  
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
8,388,608 x 8(byte mode)  
4,194,304 x 16(word mode)  
· Fast access time  
3.3V Operation : 100ns(Max.)  
3.0V Operation : 120ns(Max.)  
· Supply voltage : single +3.3V/ single +3.0V  
· Current consumption  
The KM23V64000BG is a fully static mask programmable  
ROM fabricated using silicon gate CMOS process technology,  
and is organized either as 8,388,608 x 8 bit(byte mode) or as  
4,194,304 x 16 bit(word mode) depending on BHE voltage  
level.(See mode selection table)  
This device operates with 3.0V or 3.3V power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
Operating : 40mA(Max.)  
Standby : 50mA(Max.)  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
The KM23V64000BG is packaged in a 44-SOP.  
· Package  
-. KM23V64000BG : 44-SOP-600  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A21  
X
MEMORY CELL  
MATRIX  
(4,194,304x16/  
8,388,608x8)  
A21  
A18  
A20  
1
2
44  
43  
42  
41  
40  
39  
BUFFERS  
AND  
DECODER  
.
.
.
.
.
.
.
.
A19  
A8  
A17  
A7  
3
4
A9  
A6  
A5  
A10  
A11  
5
6
Y
A4  
7
38 A12  
37 A13  
SENSE AMP.  
BUFFERS  
BUFFERS  
AND  
DECODER  
A3  
8
A14  
36  
A2  
9
A0  
A1  
A15  
35  
10  
11  
12  
13  
14  
15  
16  
17  
18  
SOP  
A16  
34  
A0  
A-1  
BHE  
CE  
VSS  
OE  
Q0  
Q8  
Q1  
Q9  
33  
32  
31  
30  
.
.
.
VSS  
Q15/A-1  
Q7  
CE  
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
29 Q14  
28 Q6  
OE  
BHE  
Q13  
Q5  
27  
26  
Q2 19  
Q10 20  
25 Q12  
Q4  
24  
Q3  
21  
22  
Pin Name  
A0 - A21  
Pin Function  
Address Inputs  
Data Outputs  
Q11  
VCC  
23  
Q0 - Q14  
KM23V64000BG  
Output 15(Word mode)/  
LSB Address(Byte mode)  
Q15 /A-1  
BHE  
CE  
Word/Byte selection  
Chip Enable  
Output Enable  
Power  
OE  
VCC  
VSS  
Ground  

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