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KM23V64000BT-12 PDF预览

KM23V64000BT-12

更新时间: 2024-11-25 21:09:35
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
4页 72K
描述
MASK ROM, 4MX16, 120ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44

KM23V64000BT-12 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2,针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
最长访问时间:120 ns其他特性:CONFIGURABLE AS 4M X 16
备用内存宽度:8JESD-30 代码:R-PDSO-G44
长度:18.41 mm内存密度:67108864 bit
内存集成电路类型:MASK ROM内存宽度:16
功能数量:1端子数量:44
字数:4194304 words字数代码:4000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX16
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

KM23V64000BT-12 数据手册

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KM23V64000BT  
CMOS MASK ROM  
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
8,388,608 x 8(byte mode)  
The KM23V64000BT is a fully static mask programmable ROM  
fabricated using silicon gate CMOS process technology, and is  
organized either as 8,388,608 x 8 bit(byte mode) or as  
4,194,304 x 16 bit(word mode) depending on BHE voltage  
level.(See mode selection table)  
4,194,304 x 16(word mode)  
· Fast access time  
3.3V Operation : 100ns(Max.)  
3.0V Operation : 120ns(Max.)  
· Supply voltage : single +3.0V/ single +3.3V  
· Current consumption  
This device operates with 3.0V or 3.3V power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
Operating : 40mA(Max.)  
Standby : 50mA(Max.)  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
The KM23V64000BT is packaged in a 44-TSOP2.  
· Package : KM23V64000BT : 44-TSOP2-400  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A21  
X
MEMORY CELL  
MATRIX  
BUFFERS  
AND  
A21  
A18  
A20  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
1
2
.
.
.
.
.
.
.
.
A19  
A8  
(4,194,304x16/  
8,388,608x8)  
A17  
A7  
3
DECODER  
4
A9  
A6  
A5  
A4  
A3  
A10  
A11  
A12  
5
6
Y
7
SENSE AMP.  
BUFFERS  
BUFFERS  
AND  
8
A13  
A14  
A15  
A2  
A1  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
DECODER  
A0  
A16  
A0  
CE  
VSS  
OE  
Q0  
TSOP2  
A-1  
BHE  
VSS  
.
.
.
Q15/A-1  
Q7  
CE  
Q8  
29 Q14  
28 Q6  
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
Q1  
OE  
Q9  
Q13  
Q5  
27  
26  
25  
24  
23  
BHE  
Q2 19  
Q10 20  
Q12  
Q4  
Q3  
21  
Q11  
22  
VCC  
Pin Name  
A0 - A21  
Pin Function  
Address Inputs  
Data Outputs  
KM23V64000BT  
Q0 - Q14  
Output 15(Word mode)/  
LSB Address(Byte mode)  
Q15 /A-1  
BHE  
CE  
Word/Byte selection  
Chip Enable  
Output Enable  
Power  
OE  
VCC  
VSS  
Ground  

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