Datasheet > IS61C64AL

IS61C64AL

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
13页	96K
描述
8K x 8 HIGH-SPEED CMOS STATIC RAM

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IS61C64AL 数据手册

IS61C64AL

ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3)(Over Operating Range)

-10ns

Min.

-12 ns

Min. Max.

Symbol

tWC

Parameter

Max

—

Unit

Write Cycle Time

CE to Write End

—

tSCS

—

tAW

Address Setup Time

to Write End

—

tHA

AddressHold

from Write End

—

tSA

Address Setup Time

—

tPWE1

tPWE2

tSD

WE Pulse Width (OE LOW)

WE Pulse Width (OE HIGH)

Data Setup to Write End

Data Hold from Write End

WE LOW to High-Z Output

WE HIGH to Low-Z Output

tHD

(2)

tHZWE

—

(2)

tLZWE

—

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the write.

AC WAVEFORMS

WRITE CYCLE NO. 1 (WE Controlled)^(1,2)

VALID ADDRESS

SCS

ADDRESS

t^PPW^WE^E2¹

HZWE

LZWE

HIGH-Z

DATA UNDEFINED

OUT

DATAIN VALID

DIN

CE_WR1.eps

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

03/16/06

1...4 5 678 9 10...13

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