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IS61C64B-12J PDF预览

IS61C64B-12J

更新时间: 2024-10-28 11:10:59
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
9页 44K
描述
8K x 8 HIGH-SPEED CMOS STATIC RAM

IS61C64B-12J 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOJ
包装说明:0.300 INCH, PLASTIC, SOJ-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.84
Is Samacsys:N最长访问时间:12 ns
其他特性:LOW POWER STANDBY MODE; AUTOMATIC POWER-DOWNI/O 类型:COMMON
JESD-30 代码:R-PDSO-J28JESD-609代码:e0
长度:18.415 mm内存密度:65536 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:28字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ28,.34封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:3.556 mm
最大待机电流:0.01 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.175 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

IS61C64B-12J 数据手册

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®
IS61C64B  
8K x 8 HIGH-SPEED CMOS STATIC RAM  
ISSI  
July 2002  
FEATURES  
DESCRIPTION  
The ISSI IS61C64B is a very high-speed, low power,  
8192-wordby8-bitstaticRAM.ItisfabricatedusingISSI'shigh-  
performance CMOS technology. This highly reliable process  
coupled with innovative circuit design techniques, yields ac-  
cess times as fast as 10 ns with low power consumption.  
• High-speed access time: 10, 12, and 15 ns  
• Automatic power-down when chip is  
deselected  
• CMOS low power operation  
— 450 mW (typical) operating  
— 250 µW (typical) standby  
• TTL compatible interface levels  
• Single 5V power supply  
WhenCEisHIGH(deselected),thedeviceassumesastandby  
mode at which the power dissipation can be reduced down to  
250 µW (typical) with CMOS input levels.  
EasymemoryexpansionisprovidedbyusingoneChipEnable  
input, CE. The active LOW Write Enable (WE) controls both  
writing and reading of the memory.  
• Fully static operation: no clock or refresh  
required  
• Three state outputs  
The IS61C64B is packaged in the JEDEC standard 28-pin,  
300-mil SOJ, and TSOP.  
• One Chip Enables (CE) for increased speed  
FUNCTIONAL BLOCK DIAGRAM  
256 X 256  
MEMORY ARRAY  
A0-A12  
DECODER  
VCC  
GND  
I/O  
DATA  
COLUMN I/O  
I/O0-I/O7  
CIRCUIT  
CE  
CONTROL  
CIRCUIT  
OE  
WE  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI  
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device  
specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. D  
07/01/02  

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