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IS61C64B-10N PDF预览

IS61C64B-10N

更新时间: 2024-11-16 23:59:47
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
7页 56K
描述
x8 SRAM

IS61C64B-10N 数据手册

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®
IS61C64B  
8K x 8 HIGH-SPEED CMOS STATIC RAM  
ISSI  
JULY 2001  
FEATURES  
DESCRIPTION  
The ISSI IS61C64B is a very high-speed, low power,  
8192-word by 8-bit static RAM. It is fabricated using ISSI's  
high-performance CMOS technology. This highly reliable pro-  
cess coupled with innovative circuit design techniques, yields  
access times as fast as 10 ns with low power consumption.  
• High-speed access time: 10, 12, and 15 ns  
• Automatic power-down when chip is  
deselected  
• CMOS low power operation  
— 450 mW (typical) operating  
— 250 µW (typical) standby  
• TTL compatible interface levels  
• Single 5V power supply  
WhenCEisHIGH(deselected),thedeviceassumesastandby  
mode at which the power dissipation can be reduced down to  
250 µW (typical) with CMOS input levels.  
Easy memory expansion is provided by using one Chip  
Enableinput, CE. TheactiveLOWWriteEnable(WE)controls  
both writing and reading of the memory.  
• Fully static operation: no clock or refresh  
required  
• Three state outputs  
The IS61C64B is packaged in the JEDEC standard 28-pin,  
300-mil DIP and SOJ, and TSOP.  
• One Chip Enables (CE) for increased speed  
FUNCTIONAL BLOCK DIAGRAM  
256 X 256  
MEMORY ARRAY  
A0-A12  
DECODER  
VCC  
GND  
I/O  
DATA  
COLUMN I/O  
I/O0-I/O7  
CIRCUIT  
CE  
CONTROL  
CIRCUIT  
OE  
WE  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any  
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
Rev. C  
07/17/01  

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