Datasheet > ICS8602BY

ICS8602BY

更新时间： 2024-09-17 21:10:03

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
11页	119K
描述
PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

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ICS8602BY 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LQFP,	针数：	32
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.22	系列：	8602
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e0	长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	9
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	240	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.125 ns	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	20
宽度：	7 mm	最小 fmax：	15.625 MHz
Base Number Matches：	1

ICS8602BY 数据手册

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS

CLOCK GENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS8602 is a high performance, low skew,

• Fully integrated PLL

,&6

1-to-9 Differential-to-LVCMOS zero delay buffer

and a member of the HiPerClockS™ family of

High Performance Clocks Solutions from ICS.

The CLK, nCLK pair can accept most standard

• 9 LVCMOS outputs, 7Ω typical output impedance

HiPerClockS™

• CLK, nCLK pair can accept the following differential

input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

differential input levels. The VCO operates at a frequency range

of 200MHz to 500MHz. The external feedback allows the de-

vice to achieve “zero delay” between the input clock and the

output clocks. The PLL_SEL pin can be used to bypass the

PLL for system test and debug purposes. In bypass mode,

the reference clock is routed around the PLL and into the in-

ternal output dividers.The low impedance LVCMOS outputs

are designed to drive 50Ω series or parallel terminated trans-

mission lines. The effective fanout can be doubled by utilizing

the ability of the outputs to drive two series terminated lines.

The differential reference clock input will accept any differen-

tial signal levels.

• Output frequency range: 12.5MHz to 250MHz

• Input frequency range: 12.5MHz to 250MHz

• VCO range: 200MHz to 500MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Cycle-to-cycle jitter: 36ps (typical)

• Output skew: 125ps (maximum)

• Static Phase Offset: TBD±100ps (typical)

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

BLOCK DIAGRAM

PIN ASSIGNMENT

SEL0

SEL1

32 31 30 29 28 27 26 25

V^DDA

VDD

V^DDO

CLK

GND

÷2

÷4

÷8

÷16

nCLK

CLK

ICS8602

GND

V^DDO

nCLK

PLL

DIV_SEL0

DIV_SEL1

GND

MR / nOE

GND

FB_IN

10 11 12 13 14 15 16

PLL_SEL

MR / nOE

32-Lead LQFP

7mm x 7mm x 1.4mm

Y Package

Top View

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

8602BY

www.icst.com/products/hiperclocks.html

REV. D JANUARY 7, 2002

12 3 4 5 6 7...11

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与ICS8602BY相关器件

型号	品牌	获取价格	描述	数据表
ICS8602BYLF	IDT	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8602BYLFT	IDT	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8602BYT	ICSI	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL
ICS8602Y	IDT	获取价格	Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H
ICS8602YLF	IDT	获取价格	Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H
ICS8602YLFT	IDT	获取价格	Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H
ICS8624	ICSI	获取价格	LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
ICS8624AYLF	IDT	获取价格	暂无描述
ICS8624AYLFT	IDT	获取价格	Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H
ICS8624AYT	IDT	获取价格	Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.4

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