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ICS8634BY-01T PDF预览

ICS8634BY-01T

更新时间: 2024-11-09 15:34:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
16页 246K
描述
PLL Based Clock Driver, 8634 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

ICS8634BY-01T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32针数:32
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.92系列:8634
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:5最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:4.2 ns传播延迟(tpd):4.2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mm最小 fmax:31.25 MHz
Base Number Matches:1

ICS8634BY-01T 数据手册

 浏览型号ICS8634BY-01T的Datasheet PDF文件第2页浏览型号ICS8634BY-01T的Datasheet PDF文件第3页浏览型号ICS8634BY-01T的Datasheet PDF文件第4页浏览型号ICS8634BY-01T的Datasheet PDF文件第5页浏览型号ICS8634BY-01T的Datasheet PDF文件第6页浏览型号ICS8634BY-01T的Datasheet PDF文件第7页 
ICS8634-01  
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY BUFFER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS8634-01 is a high performance 1-to-5 Dif-  
Five differential 3.3V LVPECL outputs  
Selectable differential clock inputs  
ICS  
ferential-to-3.3V LVPECL Zero Delay Buffer and a  
member of the HiPerClockS™ family of High Per-  
formance Clock Solutions from ICS.The ICS8634-  
01 has two selectable clock inputs. The CLKx,  
HiPerClockS™  
CLKx, nCLKx pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
nCLKx pair can accept most standard differential input levels.  
Utilizing one of the outputs as feedback to the PLL, output fre-  
quencies up to 700MHz can be regenerated with zero delay with  
respect to the input. Dual reference clock inputs support redun-  
dant clock or multiple reference applications.  
Output frequency range: 31.25MHz to 700MHz  
Input frequency range: 31.25MHz to 700MHz  
VCO range: 250MHz to 700MHz  
External feedback for “zero delay” clock regeneration  
Cycle-to-cycle jitter: 25ps (maximum)  
Output skew: 25ps (maximum)  
PLL reference zero delay: 50ps 100ps  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Lead-Free package available  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
nQ0  
PLL_SEL  
Q1  
nQ1  
÷4, ÷8  
0
32 31 30 29 28 27 26 25  
CLK0  
nCLK0  
Q2  
nQ2  
0
1
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
SEL0  
SEL1  
VCCO  
Q3  
1
CLK1  
nCLK1  
Q3  
nQ3  
CLK0  
nQ3  
Q2  
PLL  
nCLK0  
CLK1  
Q4  
nQ4  
ICS8634-01  
10 11 12 13 14 15 16  
32-Lead LQFP  
CLK_SEL  
nQ2  
Q1  
nCLK1  
CLK_SEL  
FB_IN  
nFB_IN  
nQ1  
VCCO  
MR  
9
SEL0  
SEL1  
MR  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
32-LeadVFQFN  
5mm x 5mm x 0.95 package body  
K Package  
TopView  
8634BY-01  
www.icst.com/products/hiperclocks.html  
REV.D APRIL 12, 2007  
1

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