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ICS86962CYI-01LF PDF预览

ICS86962CYI-01LF

更新时间: 2024-09-25 21:17:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
12页 167K
描述
PLL Based Clock Driver, 86962 Series, 17 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

ICS86962CYI-01LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.49其他特性:ALSO OPERATES AT 3.3V SUPPLY
系列:86962输入调节:DIFFERENTIAL
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:17最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.175 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mm最小 fmax:110 MHz
Base Number Matches:1

ICS86962CYI-01LF 数据手册

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ICS86962I-01  
Integrated  
Circuit  
Systems, Inc.  
LOW  
SKEW, 1-TO-18  
LVCMOS/LVTTL ZERO  
DELAY  
BUFFER  
GENERAL DESCRIPTION  
FEATURES  
Fully integrated PLL  
The ICS86962I-01 is a low voltage, low skew  
ICS  
LVCMOS/LVTTL Zero Delay Buffer and a mem-  
ber of the HiPerClockS™ family of High Perfor-  
mance Clock Solutions from ICS. With output  
frequencies up to 140MHz, the ICS86962I-01 is  
18 LVCMOS/LVTTL outputs:17 LVCMOS/LVTTL clock outputs,  
1 QFB feedback output. 14typical output impedance  
HiPerClockS™  
1 differential LVPECL clock pair  
targeted for high performance clock applications. Along with a  
fully integrated PLL, the ICS86962I-01 contains frequency  
configurable outputs and an external feedback input for regen-  
erating clocks with “zero delay”.  
PCLK, nPCLK pair supports the following input types:  
LVPECL, LVDS, CML, SSTL  
Input/Output frequency range: 60MHz to 140MHz  
External feedback for “zero delay” clock regeneration  
Output skew: 210ps (maximum)  
Cycle-to-cycle jitter: 100ps (maximum)  
Period jitter, RMS: 4ps (maximum)  
Full 3.3V or 2.5V supply voltage  
-40°C to 85°C ambient operating temperature  
Pin compatible to MPC961  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
PCLK  
nPCLK  
REF  
Q1  
Q2  
24 23 22 21 20 19 18 17  
PLL  
110MHz - 140MHz  
0
1
Q5  
Q4  
25  
26  
27  
28  
29  
30  
31  
32  
16  
15  
14  
13  
12  
11  
10  
9
VDD  
Q3  
Q4  
Q5  
Q6  
Q7  
Q12  
Q13  
Q14  
GND  
Q15  
Q16  
QFB  
60MHz - 110MHz  
Q3  
GND  
Q2  
ICS86962I-01  
FB_IN  
FB  
Q1  
Q0  
VDD  
F_RANGE  
1
2
3
4
5
6
7
8
Q8  
Q9  
Q10  
Q11  
Q12  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y package  
TopView  
Q13  
Q14  
Q15  
Q16  
nOE  
QFB  
86962CYI-01  
www.icst.com/products/hiperclocks.html  
REV. A DECEMBER 14, 2004  
1

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