5秒后页面跳转
ICS86953BYI PDF预览

ICS86953BYI

更新时间: 2024-01-14 00:33:42
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
13页 262K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

ICS86953BYI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.11输入调节:DIFFERENTIAL
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
电源:3.3 VProp。Delay @ Nom-Sup:7 ns
传播延迟(tpd):6 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.075 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:7 mm
最小 fmax:50 MHzBase Number Matches:1

ICS86953BYI 数据手册

 浏览型号ICS86953BYI的Datasheet PDF文件第2页浏览型号ICS86953BYI的Datasheet PDF文件第3页浏览型号ICS86953BYI的Datasheet PDF文件第4页浏览型号ICS86953BYI的Datasheet PDF文件第5页浏览型号ICS86953BYI的Datasheet PDF文件第6页浏览型号ICS86953BYI的Datasheet PDF文件第7页 
ICS86953I  
Integrated  
Circuit  
Systems, Inc.  
LOW  
SKEW, 1-TO-9  
D
IFFERENTIAL  
-
TO-LVCMOS / LVTTL ZERO  
DELAY  
BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS86953I is a low voltage, low skew 1-to-9  
Differential-to-LVCMOS/LVTTL Clock Generator  
and a member of the HiPerClockSfamily of High  
Performance Clock Solutions from ICS. The  
PCLK, nPCLK pair can accept most standard dif-  
• 9 single ended LVCMOS/LVTTL outputs;  
(8) clocks, (1) feedback  
ICS  
HiPerClockS™  
• PCLK, nPCLK pair can accept the following differential  
input levels: LVPECL, CML, SSTL  
ferential input levels. With output frequencies up to 110MHz,  
the ICS86953I is targeted for high performance clock applica-  
tions. Along with a fully integrated PLL, the ICS86953I contains  
frequency configurable outputs and an external feedback input  
for regenerating clocks with “zero delay”.  
• Maximum output frequency: PLL Mode, 110MHz  
• VCO range: 200MHz to 500MHz  
• Output skew: 75ps (maximum)  
• Cycle-to-cycle jitter: 50ps (maximum)  
• Static phase offset: 90ps 110ps  
• 3.3V supply voltage  
• -40°C to 85°C ambient operating temperature  
• Pin compatible to the MPC953  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
VDDA  
FB_CLK  
nc  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
Q1  
VDDO  
Q2  
nc  
GND  
Q3  
ICS86953I  
nc  
nc  
VDDO  
Q4  
GND  
PCLK  
GND  
9
10 11 12 13 14 15 16  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y package  
Top View  
BLOCK DIAGRAM  
QFB  
PCLK  
nPCLK  
0
1
0
1
7
Q0:Q6  
Q7  
/
0
1
Phase  
Detector  
÷4  
LPF  
VCO  
FB_CLK  
÷2  
VCO_SEL  
nBYPASS  
MR/nOE  
PLL_SEL  
86953BYI  
www.icst.com/products/hiperclocks.html  
REV. B APRIL 23, 2004  
1

与ICS86953BYI相关器件

型号 品牌 获取价格 描述 数据表
ICS86953BYI-147 ICSI

获取价格

DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
ICS86953BYI-20LF IDT

获取价格

PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953BYI-20LFT IDT

获取价格

PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953BYI-20T IDT

获取价格

PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953BYILF IDT

获取价格

PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953BYILF-147 IDT

获取价格

PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953BYILFT IDT

获取价格

PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953BYIT IDT

获取价格

PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953BYIT-147 ICSI

获取价格

DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
ICS86953I-147 ICSI

获取价格

DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER