Datasheet > ICS864S004AKIT

ICS864S004AKIT

更新时间： 2024-01-19 14:25:51

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
17页	733K
描述
Low Skew Clock Driver, 864S Series, 5 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD, VFQFN-32

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ICS864S004AKIT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	32
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.47	系列：	864S
输入调节：	DIFFERENTIAL MUX	JESD-30 代码：	S-XQCC-N32
JESD-609代码：	e0	长度：	5 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	5	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified	座面最大高度：	1 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	5 mm	最小 fmax：	18.75 MHz
Base Number Matches：	1

ICS864S004AKIT 数据手册

PRELIMINARY

LVDS ZERO DELAY BUFFER w/ JITTER ATTENUATION FOR

VIDEO APPLICATIONS

ICS864S004I

General Description

Features

The ICS864S004I is Zero-Delay Buffer with four

• Four LVDS differential output pairs, and

one feedback output pair

differential LVDS output pairs, and uses external

feedback for “zero delay” clock regeneration.

Another feature of the device is the ability to select

different bandwidth modes during normal operation

HiPerClockS™

• One differential clock input pair PCLK, nPCLK can accept the

following differential input levels: LVDS, LVPECL, CML, SSTL

• Maximum output frequency: 333.33MHz

• VCO range: 1.2GHz – 2GHz

• Cycle-to-cycle jitter: TBD

to allow for additional clock jitter attenuation.

The output frequency range is specified to include the most

common video rates used in professional video systems. With a

wide frequency range, the ICS864S004I is ideal for use in video

applications where zero-delay, low skew and jitter attenuation are

critical factors.

• 3.3V operating supply voltage

• Two bandwidth modes allow the system designer to make jitter

attenuation/tracking skew design trade-offs

• External feedback for “zero delay” clock regeneration

• -40°C to 85°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

Pin Assignment

32 31 30 29 28 27 26 25

BW_SEL

V^DDA

VDD

nQ0

nQ1

PCLK

nPCLK

SE_CLK

nQ2

nQ3

10 11 12 13 14 15 16

32-Lead VFQFN

5mm x 5mm x 0.925mm package body

K Package

Top View

The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.

Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

IDT™ / ICS™ LVDS ZERO DELAY BUFFER

ICS864S004AKI REV. A OCTOBER 10, 2007

12 3 4 5 6 7...17

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与ICS864S004AKIT相关器件

型号	品牌	获取价格	描述	数据表
ICS86953AYI-147	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953AYI-147LF	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953AYI-147T	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953AYILF	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953AYILFT	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953AYIT	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953BYI	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953BYI-147	ICSI	获取价格	DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
ICS86953BYI-20LF	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS86953BYI-20LFT	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM

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