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ICS86953BYI-147 PDF预览

ICS86953BYI-147

更新时间: 2024-09-24 02:59:07
品牌 Logo 应用领域
矽成 - ICSI 逻辑集成电路驱动
页数 文件大小 规格书
13页 263K
描述
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER

ICS86953BYI-147 数据手册

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ICS86953I-147  
Integrated  
Circuit  
Systems, Inc.  
LOW  
SKEW, 1-TO-9  
D
IFFERENTIAL  
-
TO-LVCMOS / LVTTL ZERO  
DELAY  
BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS86953I-147 is a low voltage, low skew • 9 single ended LVCMOS/LVTTL outputs;  
ICS  
1-to-9 Differential-to-LVCMOS/LVTTL Clock  
Generator and a member of the HiPerClockS™  
family of High Performance Clock Solutions from  
ICS.The PCLK, nPCLK pair can accept most stan-  
(8) clocks, (1) feedback  
HiPerClockS™  
• PCLK, nPCLK pair can accept the following differential  
input levels: LVPECL, CML, SSTL  
dard differential input levels.With output frequencies up to 175MHz,  
the ICS86953I-147 is targeted for high performance clock ap-  
plications. Along with a fully integrated PLL, the ICS86953I-147  
contains frequency configurable outputs and an external feed-  
back input for regenerating clocks with “zero delay”.  
• Maximum output frequency: PLL Mode, 175MHz  
• VCO range: 250MHz to 700MHz  
• Output skew: 75ps (maximum)  
• Cycle-to-cycle jitter: 50ps (maximum)  
• Static phase offset: 90ps 110ps  
• 3.3V supply voltage  
• -40°C to 85°C ambient operating temperature  
• Pin compatible to the MPC953  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
VDDA  
FB_CLK  
nc  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
Q1  
VDDO  
Q2  
nc  
GND  
Q3  
ICS86953I-147  
nc  
nc  
VDDO  
Q4  
GND  
PCLK  
GND  
9
10 11 12 13 14 15 16  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y package  
Top View  
BLOCK DIAGRAM  
QFB  
PCLK  
nPCLK  
0
1
0
1
7
Q0:Q6  
Q7  
/
0
1
Phase  
Detector  
÷4  
LPF  
VCO  
FB_CLK  
÷2  
VCO_SEL  
nBYPASS  
MR/nOE  
PLL_SEL  
86953BYI-147  
www.icst.com/products/hiperclocks.html  
REV. B APRIL 23, 2004  
1

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