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ICS86953AYI-147T PDF预览

ICS86953AYI-147T

更新时间: 2024-02-29 20:27:12
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
11页 122K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

ICS86953AYI-147T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.21输入调节:DIFFERENTIAL
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

ICS86953AYI-147T 数据手册

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PRELIMINARY  
ICS86953I-147  
Integrated  
Circuit  
Systems, Incꢀ  
LOW SKEW, 1-TO-9  
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS86953I-147 is a low voltage, low skew • 9 single ended LVCMOS outputs; (8) clocks, (1) feedback  
,&6  
1-to-9 Differential-to-LVCMOS clock generator and  
• Selectable differential PCLK, nPCLK or external feedback  
a member of the HiPerClockS™ family of High  
clock inputs  
HiPerClockS™  
Performance Clock Solutions from ICS. The  
PCLK, nPCLK pair can accept most standard dif-  
• FB_CLK can accept the following input levels:  
LVCMOS and LVTTL  
ferential input levels. With output frequencies up to 175MHz,  
the ICS86953I-147 is targeted for high performance clock ap-  
plications. Along with a fully integrated PLL, the ICS86953I-147  
contains frequency configurable outputs and an external feed-  
back input for regenerating clocks with “zero delay”.  
• PCLK, nPCLK pair can accept the following differential  
input levels: LVPECL, CML, SSTL  
• Maximum output frequency: PLL Mode, 175MHz  
• VCO range: 200MHz to 700MHz  
• Output skew: 75ps (typical)  
PIN ASSIGNMENT  
• Cycle-to-cycle jitter: 25ps (typical)  
• Static phase offset: 200ps (maximum)  
• 3.3V supply voltage  
• -40°C to 85°C ambient operating temperature  
• Pin compatible to the MPC953  
32 31 30 29 28 27 26 25  
VDDA  
FB_CLK  
nc  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
Q1  
VDDO  
Q2  
nc  
GND  
Q3  
ICS86953I-147  
nc  
nc  
VDDO  
Q4  
GND  
PCLK  
GND  
9
10 11 12 13 14 15 16  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y package  
Top View  
BLOCK DIAGRAM  
QFB  
PCLK  
nPCLK  
0
1
0
1
7
Q0:Q6  
Q7  
/
0
1
Phase  
Detector  
÷4  
LPF  
VCO  
FB_CLK  
÷2  
VCO_SEL  
nBYPASS  
MR/nOE  
PLL_SEL  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
86953AYI-147  
www.icst.com/products/hiperclocks.html  
REV. A MAY 10, 2002  
1

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