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ICS8634Y-01 PDF预览

ICS8634Y-01

更新时间: 2024-02-23 11:13:44
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
7页 95K
描述
PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32

ICS8634Y-01 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:5最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):3.3 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.035 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mmBase Number Matches:1

ICS8634Y-01 数据手册

 浏览型号ICS8634Y-01的Datasheet PDF文件第2页浏览型号ICS8634Y-01的Datasheet PDF文件第3页浏览型号ICS8634Y-01的Datasheet PDF文件第4页浏览型号ICS8634Y-01的Datasheet PDF文件第5页浏览型号ICS8634Y-01的Datasheet PDF文件第6页浏览型号ICS8634Y-01的Datasheet PDF文件第7页 
PRELIMINARY  
ICS8634-01  
1-TO-5 DIFFERENTIAL-TO-LVPECL  
ZERO DELAY BUFFER  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
The ICS8634-01 is a high performance LVPECL  
Fully integrated PLL  
,&6  
zero delay buffer and a member of the  
HiPerClockS™ family of High Performance  
Clocks Solutions from ICS. The VCO operates  
at a frequency range of 250MHz to 500MHz.  
5 LVPECL outputs each with the ability to drive 50to VTT  
Selectable CLK, nCLK inputs  
HiPerClockS™  
31.25MHz to 500MHz output frequency range  
Spread Smart™ for regenerating spread spectrum clocks  
Utilizing one of the outputs as feedback to the PLL output  
frequencies up to 500MHz can be regenerated with zero  
delay with respect to the input. Dual reference clock inputs  
support redundant clock or multiple reference applications.  
CLK, nCLK pair can accept the following differential input  
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
Translates any single ended input signal (LVCMOS, LVTTL,  
GTL) to 3.3V LVPECL levels with resistor bias on nCLK  
input  
31.25MHz to 500MHz input frequency range  
3.3V operating supply voltage  
32 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm  
package body, 0.8mm package lead pitch  
0°C to 70°C ambient operating temperature  
Industrial temperature version available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
DIV_SEL0  
DIV_SEL1  
32 31 30 29 28 27 26 25  
Q0  
nQ0  
Q1  
nQ1  
Q2  
nQ2  
Q3  
nQ3  
Q4  
nQ4  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
DIV_SEL0  
DIV_SEL1  
CLK1  
VDDO  
Q3  
÷1  
÷2  
÷4  
CLK1  
nQ3  
Q2  
0
0
1
nCLK1  
nCLK1  
ICS8634-01  
1
CLK2  
PLL  
÷8  
CLK2  
nQ2  
Q1  
nCLK2  
nCLK2  
REF_SEL  
REF_SEL  
nQ1  
VDDO  
FB_IN  
MR  
nFB_IN  
9
10 11 12 13 14 15 16  
PLL_SEL  
MR  
32-Lead LQFP  
Y Package  
Top View  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8634-01  
www.icst.com/products/hiperclocks.html  
REV. C JUNE 20, 2001  
1

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