Datasheet > ICS8602BYT

ICS8602BYT

更新时间： 2024-02-15 08:46:48

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
10页	149K
描述
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

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ICS8602BYT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Transferred	零件包装代码：	QFP
包装说明：	7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32	针数：	32
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.38	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	7 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	9
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.125 ns	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm	最小 fmax：	225 MHz

ICS8602BYT 数据手册

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS8602 is a high performance, low skew,

• Fully integrated PLL

,&6

1-to-9 Differential-to-LVCMOS/LVTTL Zero De-

• 9 LVCMOS/LVTTL outputs, 7Ω typical output impedance

HiPerClockS™

lay Buffer and a member of the HiPerClockS™

family of High Performance Clocks Solutions

from ICS. The CLK, nCLK pair can accept most

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

standard differential input levels. The VCO operates at a fre-

quency range of 250MHz to 500MHz. The external feedback

allows the device to achieve “zero delay” between the input

clock and the output clocks. The device is designed only for

1:1 input/output frequency ratios. The output divider allows a

wide input/output frequency range with the 250MHz to

500MHz VCO. The PLL_SEL pin can be used to bypass the

PLL for system test and debug purposes. In bypass mode,

the reference clock is routed around the PLL and into the in-

ternal output dividers.The low impedance LVCMOS/LVTTL out-

puts are designed to drive 50Ω series or parallel terminated

transmission lines. The effective fanout can be doubled by

utilizing the ability of the outputs to drive two series termi-

nated lines. The differential reference clock input will accept

any differential signal levels.

• Output frequency range: 15.625MHz to 250MHz

• Input frequency range: 15.625MHz to 250MHz

• VCO range: 250MHz to 500MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Cycle-to-cycle jitter: 36ps (typical)

• Output skew: 125ps (maximum)

• Static Phase Offset: TBD±100ps (typical)

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

BLOCK DIAGRAM

PIN ASSIGNMENT

SEL0

SEL1

32 31 30 29 28 27 26 25

V^DDA

VDD

V^DDO

CLK

GND

÷2

÷4

÷8

÷16

nCLK

CLK

ICS8602

GND

V^DDO

nCLK

PLL

DIV_SEL0

DIV_SEL1

GND

MR/nOE

GND

FB_IN

10 11 12 13 14 15 16

PLL_SEL

MR/nOE

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

12 3 4 5 6 7...10

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与ICS8602BYT相关器件

型号	品牌	描述	获取价格	数据表
ICS8602Y	IDT	Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H	获取价格
ICS8602YLF	IDT	Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H	获取价格
ICS8602YLFT	IDT	Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H	获取价格
ICS8624	ICSI	LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER	获取价格
ICS8624AYLF	IDT	暂无描述	获取价格
ICS8624AYLFT	IDT	Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H	获取价格

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