5秒后页面跳转
ICS8624BYLFT PDF预览

ICS8624BYLFT

更新时间: 2024-11-08 22:09:27
品牌 Logo 应用领域
矽成 - ICSI 逻辑集成电路驱动
页数 文件大小 规格书
16页 288K
描述
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

ICS8624BYLFT 数据手册

 浏览型号ICS8624BYLFT的Datasheet PDF文件第2页浏览型号ICS8624BYLFT的Datasheet PDF文件第3页浏览型号ICS8624BYLFT的Datasheet PDF文件第4页浏览型号ICS8624BYLFT的Datasheet PDF文件第5页浏览型号ICS8624BYLFT的Datasheet PDF文件第6页浏览型号ICS8624BYLFT的Datasheet PDF文件第7页 
ICS8624  
Integrated  
Circuit  
Systems, Inc.  
L
OW  
SKEW, 1-TO-5  
D
IFFERENTIAL  
-
TO-HSTL ZERO  
DELAY  
BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8624 is a high performance, 1-to-5  
Fully integrated PLL  
ICS  
Differential-to-HSTL zero delay buffer and  
a member of the HiPerClockS™ family of High  
Performance Clock Solutions from ICS. The  
ICS8624 has two selectable clock input pairs.  
5 differential HSTL outputs  
HiPerClockS™  
Selectable differential CLKx, nCLKx input pairs  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL  
The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most  
standard differential input levels.The VCO operates at a fre-  
quency range of 250MHz to 700MHz. Utilizing one of the  
outputs as feedback to the PLL, output frequencies up to  
700MHz can be regenerated with zero delay with respect to  
the input. Dual reference clock inputs support redundant clock  
or multiple reference applications.  
Output frequency range: 31.25MHz to 700MHz  
Input frequency range: 31.25MHz to 700MHz  
VCO range: 250MHz to 700MHz  
External feedback for “zero delay” clock regeneration  
Cycle-to-cycle jitter: 25ps (maximum)  
Output skew: 25ps (maximum)  
Static phase offset: 100ps  
3.3V core, 1.8V output operating supply  
0°C to 70°C ambient operating temperature  
Lead-Free package available  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
nQ0  
PLL_SEL  
Q1  
nQ1  
÷4, ÷8  
0
1
32 31 30 29 28 27 26 25  
CLK0  
nCLK0  
Q2  
nQ2  
0
1
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
SEL0  
SEL1  
VDDO  
Q3  
CLK1  
nCLK1  
Q3  
nQ3  
CLK0  
nQ3  
Q2  
PLL  
nCLK0  
CLK1  
Q4  
nQ4  
CLK_SEL  
ICS8624  
nQ2  
Q1  
nCLK1  
CLK_SEL  
MR  
FB_IN  
nFB_IN  
nQ1  
VDDO  
9
10 11 12 13 14 15 16  
SEL0  
SEL1  
MR  
32-Lead LQFP  
7mm x 7mm x 1.4mm body package  
Y Package  
TopView  
8624BY  
www.icst.com/products/hiperclocks.html  
REV. C JUNE 15, 2004  
1

与ICS8624BYLFT相关器件

型号 品牌 获取价格 描述 数据表
ICS8624BYT ICSI

获取价格

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
ICS8624I IDT

获取价格

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
ICS8633AF-01 IDT

获取价格

PLL Based Clock Driver, 8633 Series, 3 True Output(s), 0 Inverted Output(s), PDSO28, 5.30
ICS8633AF-01LF IDT

获取价格

PLL Based Clock Driver, 8633 Series, 3 True Output(s), 0 Inverted Output(s), PDSO28, 5.30
ICS8633AF-01LFT IDT

获取价格

PLL Based Clock Driver, 8633 Series, 3 True Output(s), 0 Inverted Output(s), PDSO28, 5.30
ICS8634BK-01 IDT

获取价格

PLL Based Clock Driver, 8634 Series, 5 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.9
ICS8634BK-01LF IDT

获取价格

PLL Based Clock Driver, 8634 Series, 5 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.9
ICS8634BK-01LFT IDT

获取价格

PLL Based Clock Driver, 8634 Series, 5 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.9
ICS8634BK-01T IDT

获取价格

PLL Based Clock Driver, 8634 Series, 5 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.9
ICS8634BY-01 IDT

获取价格

PLL Based Clock Driver, 8634 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7