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ICS8633AF-01LF PDF预览

ICS8633AF-01LF

更新时间: 2024-02-29 03:06:38
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 187K
描述
PLL Based Clock Driver, 8633 Series, 3 True Output(s), 0 Inverted Output(s), PDSO28, 5.30 X 10.20 MM, 1.75 MM HEIGHT, ROHS COMPLIANT, MO-150, SSOP-28

ICS8633AF-01LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:5.30 X 10.20 MM, 1.75 MM HEIGHT, ROHS COMPLIANT, MO-150, SSOP-28针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82系列:8633
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:10.2 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:28实输出次数:3
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:4.9 ns
传播延迟(tpd):4.9 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.025 ns座面最大高度:2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:5.3 mm
最小 fmax:31.25 MHzBase Number Matches:1

ICS8633AF-01LF 数据手册

 浏览型号ICS8633AF-01LF的Datasheet PDF文件第2页浏览型号ICS8633AF-01LF的Datasheet PDF文件第3页浏览型号ICS8633AF-01LF的Datasheet PDF文件第4页浏览型号ICS8633AF-01LF的Datasheet PDF文件第5页浏览型号ICS8633AF-01LF的Datasheet PDF文件第6页浏览型号ICS8633AF-01LF的Datasheet PDF文件第7页 
ICS8633-01  
1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY BUFFER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS8633-01 is a high performance 1-to-3  
Three differential 3.3V LVPECL outputs  
Selectable differential clock inputs  
ICS  
Differential-to-3.3V LVPECL Zero Delay Buffer  
and a member of the HiPerClockS™ family of  
High Performance Clock Solutions from ICS.  
The ICS8633-01 has two selectable clock in-  
HiPerClockS™  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
puts. The CLKx, nCLKx pairs can accept most standard  
differential input levels. Utilizing one of the outputs as feed-  
back to the PLL, output frequencies up to 700MHz can be  
regenerated with zero delay with respect to the input. Dual  
reference clock inputs support redundant clock or multiple  
reference applications.  
Output frequency range: 31.25MHz to 700MHz  
Input frequency range: 31.25MHz to 700MHz  
VCO range: 250MHz to 700MHz  
External feedback for “zero delay” clock regeneration  
Cycle-to-cycle jitter: 25ps (maximum)  
Output skew: 25ps (maximum)  
PLL reference zero delay: 50ps 100ps  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
Available in both standard and lead-free RoHs-compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
PLL_SEL  
Q0  
1
2
3
4
PLL_SEL  
VCC  
28  
27  
26  
25  
VCCA  
VEE  
VEE  
VCCO  
VCCO  
Q2  
nQ2  
Q1  
nQ0  
÷4, ÷8  
0
CLK0  
nCLK0  
SEL0  
SEL1  
Q1  
nQ1  
0
1
1
CLK0  
nCLK0  
CLK1  
24  
23  
22  
21  
20  
19  
5
6
7
8
CLK1  
nCLK1  
Q2  
nQ2  
PLL  
nCLK1  
CLK_SEL  
CLK_SEL  
MR  
nQ1  
Vcco  
Vcco  
Q0  
nQ0  
VEE  
9
10  
11  
12  
13  
FB_IN  
nFB_IN  
VCC  
18  
17  
16  
15  
nFB_IN  
FB_IN  
VEE  
14  
SEL0  
SEL1  
MR  
ICS8633-01  
28-Lead, 209-MIL SSOP  
5.3mm x 10.2mm x 1.75mm body package  
F Package  
TopView  
8633AF-01  
www.icst.com/products/hiperclocks.html  
REV.A JANUARY 26, 2006  
1

ICS8633AF-01LF 替代型号

型号 品牌 替代类型 描述 数据表
8735AY-31LFT IDT

功能相似

1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator
8735AY-31LF IDT

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1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator
8634BY-01LF IDT

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TQFP-32, Tray

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