Datasheet > ICS8602BYLF

ICS8602BYLF

更新时间： 2024-01-30 21:47:38

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
10页	171K
描述
PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

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ICS8602BYLF 数据手册

PRELIMINARY

ICS8602

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS8602 is a high performance, low skew,

• Fully integrated PLL

ICS

1-to-9 Differential-to-LVCMOS/LVTTL Zero De-

• 9 LVCMOS/LVTTL outputs, 7Ω typical output impedance

HiPerClockS™

lay Buffer and a member of the HiPerClockS™

family of High Performance Clocks Solutions

from IDT.The CLK, nCLK pair can accept most

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

standard differential input levels.The VCO operates at a fre-

quency range of 250MHz to 500MHz. The external feedback

allows the device to achieve “zero delay” between the input

clock and the output clocks. The device is designed only for

1:1 input/output frequency ratios.The output divider allows a

wide input/output frequency range with the 250MHz to

500MHz VCO. The PLL_SEL pin can be used to bypass the

PLL for system test and debug purposes. In bypass mode,

the reference clock is routed around the PLL and into the in-

ternal output dividers.The low impedance LVCMOS/LVTTL out-

puts are designed to drive 50Ω series or parallel terminated

transmission lines. The effective fanout can be doubled by

utilizing the ability of the outputs to drive two series termi-

nated lines.The differential reference clock input will accept

any differential signal levels.

• Output frequency range: 15.625MHz to 250MHz

• Input frequency range: 15.625MHz to 250MHz

• VCO range: 250MHz to 500MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Cycle-to-cycle jitter: 36ps (typical)

• Output skew: 125ps (maximum)

• Static Phase Offset: TBD±100ps (typical)

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Available in both standard (RoHS5) and lead-free (RoHS 6)

packages

BLOCK DIAGRAM

PIN ASSIGNMENT

SEL0

SEL1

32 31 30 29 28 27 26 25

V^DDA

VDD

V^DDO

CLK

GND

÷2

÷4

÷8

nCLK

CLK

ICS8602

GND

V^DDO

nCLK

PLL

÷16

DIV_SEL0

DIV_SEL1

GND

MR/nOE

GND

FB_IN

10 11 12 13 14 15 16

PLL_SEL

MR/nOE

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

TopView

The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product

characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifica-

tions without notice.

8602BY

REV.F JANUARY 16, 2008

12 3 4 5 6 7...10

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与ICS8602BYLF相关器件

型号	品牌	描述	获取价格	数据表
ICS8602BYLFT	IDT	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM	获取价格
ICS8602BYT	ICSI	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL	获取价格
ICS8602Y	IDT	Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H	获取价格
ICS8602YLF	IDT	Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H	获取价格
ICS8602YLFT	IDT	Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H	获取价格
ICS8624	ICSI	LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER	获取价格

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