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ICS8602AYT PDF预览

ICS8602AYT

更新时间: 2024-11-07 15:34:35
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
7页 95K
描述
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32

ICS8602AYT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.22输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:9
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.125 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

ICS8602AYT 数据手册

 浏览型号ICS8602AYT的Datasheet PDF文件第2页浏览型号ICS8602AYT的Datasheet PDF文件第3页浏览型号ICS8602AYT的Datasheet PDF文件第4页浏览型号ICS8602AYT的Datasheet PDF文件第5页浏览型号ICS8602AYT的Datasheet PDF文件第6页浏览型号ICS8602AYT的Datasheet PDF文件第7页 
PRELIMINARY  
ICS8602  
Integrated  
Circuit  
Systems, Incꢀ  
LOW SKEW, 1-TO-9  
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8602 is a high performance LVCMOS  
Fully integrated PLL  
,&6  
zero delay buffer and a member of the  
9 LVCMOS outputs  
HiPerClockS™  
HiPerClockS™ family of High Performance  
Clocks Solutions from ICS. The VCO operates  
at a frequency range of 250MHz to 450MHz.  
15.625MHz to 225MHz output frequency range  
Spread Smart™ for regenerating spread spectrum clocks  
Utilizing one of the outputs as feedback to the PLL output  
frequencies up to 225MHz can be regenerated with zero  
delay with respect to the input. The low impedance  
LVCMOS outputs are designed to drive 50series or  
parallel terminated transmission lines. The effective fan-  
out can be doubled by utilizing the ability of the outputs to  
drive two series terminated lines. The differential reference  
clock input will accept any differential signal levels.  
Differential reference clock input accepts any differential  
signal levels  
15.625MHz to 225MHz input frequency range  
LVCMOS / LVTTL control inputs  
3.3V supply voltage  
32 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm  
package body, 0.8mm package lead pitch  
0°C to 70°C ambient operating temperature  
Industrial temperature version available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
DIV_SEL0  
DIV_SEL1  
32 31 30 29 28 27 26 25  
VDDA  
VDDI  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
VDDO  
Q5  
÷2  
÷4  
÷8  
÷16  
REF_CLK  
nREF_CLK  
GND  
GND  
Q4  
0
REF_CLK  
ICS8602  
nREF_CLK  
1
PLL  
VDDO  
Q3  
DIV_SEL0  
DIV_SEL1  
GND  
MR / nOE  
GND  
FB_IN  
9
10 11 12 13 14 15 16  
PLL_SEL  
MR / nOE  
32-Lead LQFP  
Y Package  
Top View  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8602  
www.icst.com/products/hiperclocks.html  
REV. C MAY 3, 2001  
1

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