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FQU2P25

更新时间： 2024-11-20 22:18:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
9页 536K
描述
250V P-Channel MOSFET

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中文翻译

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FQU2P25 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TO-251包装说明：IN-LINE, R-PSIP-T3
针数：3Reach Compliance Code：unknown
ECCN代码：EAR99风险等级：5.88
雪崩能效等级（Eas）：120 mJ配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：250 V最大漏极电流 (Abs) (ID)：2 A
最大漏极电流 (ID)：2 A最大漏源导通电阻：4 Ω
FET 技术：METAL-OXIDE SEMICONDUCTORJEDEC-95代码：TO-251
JESD-30 代码：R-PSIP-T3JESD-609代码：e0
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：P-CHANNEL最大功率耗散 (Abs)：37 W
最大脉冲漏极电流 (IDM)：8 A认证状态：Not Qualified
子类别：Other Transistors表面贴装：NO
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子位置：SINGLE处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON

FQU2P25 数据手册

 浏览型号FQU2P25的Datasheet PDF文件第2页浏览型号FQU2P25的Datasheet PDF文件第3页浏览型号FQU2P25的Datasheet PDF文件第4页浏览型号FQU2P25的Datasheet PDF文件第5页浏览型号FQU2P25的Datasheet PDF文件第6页浏览型号FQU2P25的Datasheet PDF文件第7页 
                                                                                                                                                                                                                                                                  
                                                                                                              
                                                                                                              
                                                                                                                 
                                                                                                                 
                                                                                                                                                                                                                                                                  
                                                                                                                                                                                                                                                                  
April 2000  
TM  
QFET  
FQD2P25 / FQU2P25  
250V P-Channel MOSFET  
General Description  
Features  
These P-Channel enhancement mode power field effect  
transistors are produced using Fairchild’s proprietary,  
planar stripe, DMOS technology.  
This advanced technology has been especially tailored to  
minimize on-state resistance, provide superior switching  
performance, and withstand high energy pulse in the  
avalanche and commutation mode. These devices are well  
suited for high efficiency switching DC/DC converters.  
•
•
•
•
•
•
-2.0A, -250V, R  
= 4.0Ω @V = -10 V  
DS(on) GS  
Low gate charge ( typical 6.5 nC)  
Low Crss ( typical 6.5 pF)  
Fast switching  
100% avalanche tested  
Improved dv/dt capability  
D
S
!
ꢀ
ꢀ
G!  
ꢁ
ꢀ
I-PAK  
FQU Series  
D-PAK  
FQD Series  
ꢀ
G
S
G
D
S
!
D
Absolute Maximum Ratings  
ꢀꢀ  
T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
FQD2P25 / FQU2P25  
Units  
V
V
I
Drain-Source Voltage  
-250  
-2.0  
DSS  
- Continuous (T = 25°C)  
Drain Current  
A
D
C
- Continuous (T = 100°C)  
-1.27  
-8.0  
A
C
I
(Note 1)  
Drain Current  
- Pulsed  
A
DM  
V
E
I
Gate-Source Voltage  
±ꢀ30  
120  
V
GSS  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
Single Pulsed Avalanche Energy  
Avalanche Current  
mJ  
A
AS  
-2.0  
AR  
E
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
3.7  
mJ  
V/ns  
W
AR  
dv/dt  
-5.5  
Power Dissipation (T = 25°C) *  
2.5  
P
A
D
Power Dissipation (T = 25°C)  
37  
W
C
- Derate above 25°C  
Operating and Storage Temperature Range  
0.29  
-55 to +150  
W/°C  
°C  
T , T  
J
STG  
Maximum lead temperature for soldering purposes,  
T
300  
°C  
L
1/8ꢀꢁfrom case for 5 seconds  
Thermal Characteristics  
Symbol  
Parameter  
Typ  
--  
Max  
3.4  
50  
Units  
°CꢁW  
°CꢁW  
°CꢁW  
R
R
R
Thermal Resistance, Junction-to-Case  
Thermal Resistance, Junction-to-Ambient *  
Thermal Resistance, Junction-to-Ambient  
θ
θ
θ
JC  
JA  
JA  
--  
--  
110  
* When mounted on the minimum pad size recommended (PCB Mount)  
©2000 Fairchild Semiconductor International  
Rev. A, April 2000  
1234567...9

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