March 2008
®
QFET
FQD3N50C / FQU3N50C
500V N-Channel MOSFET
Features
Description
•
•
•
•
•
•
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2.5A, 500V, RDS(on) = 2.5Ω @VGS = 10 V
Low gate charge ( typical 10 nC)
Low Crss ( typical 8.5pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
RoHS compliant
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies, active power factor
correction, electronic lamp ballast based on half bridge
topology.
D
D
G
I-PAK
FQU Series
D-PAK
FQD Series
G
S
G D S
S
Absolute Maximum Ratings
Symbol
Parameter
Units
V
FQD3N50C/FQU3N50C
VDSS
ID
Drain-Source Voltage
500
2.5
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
- Pulsed
A
1.5
A
(Note 1)
IDM
Drain Current
10
A
VGSS
EAS
IAR
Gate-Source Voltage
± 30
200
V
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
2.5
EAR
dv/dt
PD
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
3.5
mJ
V/ns
W
4.5
35
- Derate above 25°C
0.28
-55 to +150
W/°C
°C
TJ, TSTG
TL
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
300
°C
Thermal Characteristics
Symbol
Parameter
Typ
Max
3.5
Units
°C/W
°C/W
°C/W
RθJC
RθJA
RθJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient*
Thermal Resistance, Junction-to-Ambient
--
--
--
50
110
* When mounted on the minimum pad size recommended (PCB Mount)
©2008 Fairchild Semiconductor Corporation
FQD3N50C / FQU3N50C Rev. B
1
www.fairchildsemi.com