Datasheet > CY62138FV30_11

CY62138FV30_11

更新时间： 2024-11-05 09:42:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	672K
描述
2-Mbit (256 K x 8) Static RAM Automatic power down when deselected

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CY62138FV30_11 数据手册

CY62138FV30 MoBL^®

2-Mbit (256 K × 8) Static RAM

2-Mbit (256

K × 8) Static RAM

Features

Functional Description

■ Very high-speed: 45 ns

The CY62138FV30 is a high performance CMOS static RAM

organized as 256K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption. Place the device into standby mode reducing

power consumption when deselected (CE₁HIGH or CE₂LOW).

■ Temperature ranges

❐ Industrial: –40 °C to 85 °C

❐ Automotive-A: –40 °C to 85 °C

■ Wide voltage range: 2.20 V to 3.60 V

■ Pin compatible with CY62138CV25/30/33

To write to the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location specified

on the address pins (A₀through A₁₇).

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 5 A

■ Ultra low active power

❐ Typical active current: 1.6 mA at f = 1 MHz

To read from the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ Easy memory expansion with CE₁, CE₂, and OE Features

■ Automatic power down when deselected

The eight input and output pins (I/O₀through I/O₇) are placed in

a high impedance state when the device is deselected (CE₁

HIGH or CE₂LOW), the outputs are disabled (OE HIGH), or

during a write operation (CE₁LOW and CE₂HIGH and WE

LOW).

■ Complementary metal oxide semiconductor (CMOS) for

Optimum speed and power

■ Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin

SOIC, 32-pin TSOP I and 32-pin STSOP packages

Logic Block Diagram

Cypress Semiconductor Corporation

Document #: 001-08029 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 16, 2011

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与CY62138FV30_11相关器件

型号	品牌	获取价格	描述	数据表
CY62138FV30LL	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45BVXI	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62138FV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62138FV30LL-45SXI	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45SXIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62138FV30LL-45ZAXA	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45ZAXA	INFINEON	获取价格	Asynchronous SRAM
CY62138FV30LL-45ZAXAT	CYPRESS	获取价格	暂无描述
CY62138FV30LL-45ZAXAT	INFINEON	获取价格	Asynchronous SRAM

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