Datasheet > CY62138FV30LL-45ZXIT

CY62138FV30LL-45ZXIT

更新时间： 2024-09-14 14:56:11

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
20页	727K
描述
Asynchronous SRAM

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中文翻译

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数据手册

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CY62138FV30LL-45ZXIT 数据手册

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CY62138FV30 MoBL^®

2-Mbit (256 K × 8) Static RAM

2-Mbit (256

K × 8) Static RAM

Features

Functional Description

■ Very high-speed: 45 ns

The CY62138FV30 is a high performance CMOS static RAM

organized as 256K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption. Place the device into standby mode reducing

power consumption when deselected (CE₁HIGH or CE₂LOW).

■ Temperature ranges

❐ Industrial: –40 °C to 85 °C

❐ Automotive-A: –40 °C to 85 °C

■ Wide voltage range: 2.20 V to 3.60 V

■ Pin compatible with CY62138CV25/30/33

To write to the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location specified

on the address pins (A₀through A₁₇).

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 5 A

■ Ultra low active power

❐ Typical active current: 1.6 mA at f = 1 MHz

To read from the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ Easy memory expansion with CE₁, CE₂, and OE Features

■ Automatic power down when deselected

The eight input and output pins (I/O₀through I/O₇) are placed in

a high impedance state when the device is deselected (CE₁

HIGH or CE₂LOW), the outputs are disabled (OE HIGH), or

during a write operation (CE₁LOW and CE₂HIGH and WE

LOW).

■ Complementary metal oxide semiconductor (CMOS) for

Optimum speed and power

■ Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin

SOIC, 32-pin TSOP I and 32-pin STSOP packages

Logic Block Diagram

Cypress Semiconductor Corporation

Document Number: 001-08029 Rev. *N

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 12, 2014

12 3 4 5 6 7...20

中文翻译

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