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CY62138FV30LL-45BVXIT PDF预览

CY62138FV30LL-45BVXIT

更新时间： 2024-11-06 14:56:11
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
20页 727K
描述
Asynchronous SRAM

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CY62138FV30LL-45BVXIT 数据手册

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CY62138FV30 MoBL®  
2-Mbit (256 K × 8) Static RAM  
2-Mbit (256  
K × 8) Static RAM  
Features  
Functional Description  
■ Very high-speed: 45 ns  
The CY62138FV30 is a high performance CMOS static RAM  
organized as 256K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption. Place the device into standby mode reducing  
power consumption when deselected (CE1 HIGH or CE2 LOW).  
■ Temperature ranges  
❐ Industrial: –40 °C to 85 °C  
❐ Automotive-A: –40 °C to 85 °C  
■ Wide voltage range: 2.20 V to 3.60 V  
■ Pin compatible with CY62138CV25/30/33  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location specified  
on the address pins (A0 through A17).  
■ Ultra low standby power  
❐ Typical standby current: 1 A  
❐ Maximum standby current: 5 A  
■ Ultra low active power  
❐ Typical active current: 1.6 mA at f = 1 MHz  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appear on the I/O pins.  
■ Easy memory expansion with CE1, CE2, and OE Features  
■ Automatic power down when deselected  
The eight input and output pins (I/O0 through I/O7) are placed in  
a high impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW and CE2 HIGH and WE  
LOW).  
■ Complementary metal oxide semiconductor (CMOS) for  
Optimum speed and power  
■ Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin  
SOIC, 32-pin TSOP I and 32-pin STSOP packages  
Logic Block Diagram  
Cypress Semiconductor Corporation  
Document Number: 001-08029 Rev. *N  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 12, 2014  
1234567...20

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与CY62138FV30LL-45BVXIT相关器件

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CY62138FV30LL-45SXI CYPRESS

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 		2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45SXIT CYPRESS

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 		Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62138FV30LL-45ZAXA CYPRESS

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 		2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45ZAXA INFINEON

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 		Asynchronous SRAM
CY62138FV30LL-45ZAXAT CYPRESS

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 		暂无描述
CY62138FV30LL-45ZAXAT INFINEON

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 		Asynchronous SRAM
CY62138FV30LL-45ZAXI CYPRESS

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 		2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45ZAXI INFINEON

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 		Asynchronous SRAM
CY62138FV30LL-45ZAXIT CYPRESS

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 		Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, 1.20 MM HEIGHT, LEAD FREE, STSOP-
CY62138FV30LL-45ZAXIT INFINEON

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 		Asynchronous SRAM

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