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CY62138VL-70BAI PDF预览

CY62138VL-70BAI

更新时间: 2024-11-23 20:08:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
8页 171K
描述
Standard SRAM, 256KX8, 70ns, CMOS, PBGA36

CY62138VL-70BAI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
Is Samacsys:N最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B36
JESD-609代码:e0内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
端子数量:36字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装等效代码:BGA36,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, FINE PITCH并行/串行:PARALLEL
电源:3 V认证状态:Not Qualified
最大待机电流:0.000001 A最小待机电流:1 V
子类别:SRAMs最大压摆率:0.015 mA
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
Base Number Matches:1

CY62138VL-70BAI 数据手册

 浏览型号CY62138VL-70BAI的Datasheet PDF文件第2页浏览型号CY62138VL-70BAI的Datasheet PDF文件第3页浏览型号CY62138VL-70BAI的Datasheet PDF文件第4页浏览型号CY62138VL-70BAI的Datasheet PDF文件第5页浏览型号CY62138VL-70BAI的Datasheet PDF文件第6页浏览型号CY62138VL-70BAI的Datasheet PDF文件第7页 
CY62138V MoBL™  
256K x 8 Static RAM  
sumption by 99% when addresses are not toggling. The device  
Features  
can be put into standby mode when deselected (CS HIGH or  
1
• Low voltage range:  
— 2.7–3.6V  
CS LOW).  
2
Writing to the device is accomplished by taking Chip Enable  
One (CS ) and Write Enable (WE) inputs LOW and Chip En-  
• Ultra-low active power  
• Low standby power  
• Easy memory expansion with CS /CS and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
1
able Two (CS ) HIGH. Data on the eight I/O pins (I/O through  
2
0
I/O ) is then written into the location specified on the address  
7
1
2
pins (A through A ).  
0
17  
Reading from the device is accomplished by taking Chip En-  
able One (CS ) and Output Enable (OE) LOW while forcing  
1
Write Enable (WE) and Chip Enable Two (CS ) HIGH. Under  
2
these conditions, the contents of the memory location speci-  
fied by the address pins will appear on the I/O pins.  
Functional Description  
The eight input/output pins (I/O through I/O ) are placed in a  
The CY62138V is a high-performance CMOS static RAM or-  
ganized as 262,144 words by 8 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL™) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that reduces power con-  
0
7
high-impedance state when the device is deselected (CS  
1
HIGH or CS LOW), the outputs are disabled (OE HIGH), or  
2
during a write operation (CS LOW, CS HIGH, and WE LOW).  
1
2
The CY62138V is available in a 36-ball FBGA.  
Logic Block Diagram  
Pin Configuration  
FBGA  
TOP View  
1
2
4
3
5
6
A8  
I/O  
A
A
A1  
A2  
CS2  
A 0  
I/O  
6
A
B
C
3
I/O  
0
Data in Drivers  
A
WE  
NC  
A7  
4
0
4
I/O  
I/O  
1
2
3
4
5
A
A
A
0
1
2
3
4
5
6
A
I/O  
I/O  
1
5
5
A
A
A
A
I/O  
I/O  
I/O  
V
V
256K x 8  
ARRAY  
D
E
F
CC  
SS  
A
7
8
V
CC  
V
SS  
A
NC  
CS  
A
I/O  
I/O  
2
17  
6
I/O  
POWER  
DOWN  
6
7
COLUMN  
DECODER  
CS  
1
2
CS  
A
G
H
I/O  
1
I/O  
3
OE  
A
A
15  
I/O  
16  
7
WE  
62138V-1  
OE  
A
A
A
13  
A14  
A9  
12  
11  
10  
62138V–2  
More Battery Life and MoBL are trademarks of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
January 20, 2000  

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