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CY62146CV18LL-70BAI PDF预览

CY62146CV18LL-70BAI

更新时间: 2024-11-06 04:34:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
12页 294K
描述
Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48

CY62146CV18LL-70BAI 数据手册

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CY62146CV18 MoBL2™  
256K x 16 Static RAM  
reduces power consumption by 99% when addresses are not  
toggling. The device can also be put into standby mode when  
deselected (CE HIGH). The input/output pins (I/O0 through  
I/O15) are placed in a high-impedance state when deselected  
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
Features  
High Speed  
55 ns and 70 ns availability  
Low voltage range:  
1.65V1.95V  
Pin Compatible with CY62146BV18  
Ultra-low active power  
Typical Active Current: 0.5 mA @ f = 1 MHz  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
Typical Active Current: 2 mA @ f = fmax (70 ns speed)  
Low standby power  
Easy memory expansion with CE and OE features  
Automatic power-down when deselected  
CMOS for optimum speed/power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
Functional Description  
The CY62146CV18 is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. These devices feature  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life(MoBL) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
The CY62146CV18 is available in a 48-Ball FBGA package.  
Logic Block Diagram  
DATA IN DRIVERS  
A
A
A
9
8
7
6
A
A
A
A
256K x 16  
5
4
RAM Array  
I/O I/O  
0
7
2048 x 2048  
3
2
I/O I/O  
A
8
15  
A
A
1
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05010 Rev. *C  
Revised August 28, 2002  

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