Datasheet > CY62146CV30LL-70BVIT

CY62146CV30LL-70BVIT

更新时间： 2024-09-16 08:34:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
12页	288K
描述
Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48

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CY62146CV30 MoBL™

256K x 16 Static RAM

power consumption by 80% when addresses are not toggling.

The device can also be put into standby mode reducing power

consumption by 99% when deselected (CE HIGH). The in-

put/output pins (I/O₀–I/O₁₅) are placed in a high-impedance

state when: deselected (CE HIGH), outputs are disabled (OE

HIGH), both Byte High Enable and Byte Low Enable are dis-

abled (BHE, BLE HIGH), or during a Write operation (CE LOW

and WE LOW).

Features

• High speed:

— 55 ns and 70 ns availability

• Voltage range:

— CY62146CV30: 2.7V – 3.3V

• Pin compatible with CY62146V

• Ultra-low active power

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀–I/O₇), is written

into the location specified on the address pins (A₀–A₁₇). If Byte

High Enable (BHE) is LOW, then data from I/O pins

(I/O₈–I/O₁₅) is written into the location specified on the ad-

dress pins (A₀–A₁₇).

— Typical active current: 1.5 mA @ f = 1 MHz

— Typicalactivecurrent:5.5mA@f=f_max(70nsspeed)

• Low standby power

• Easy memory expansion with CE and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then

data from the memory location specified by the address pins

will appear on I/O₀–I/O₇. If Byte High Enable (BHE) is LOW,

then data from memory will appear on I/O₈to I/O₁₅. See the

Truth Table on page 9 for a complete description of Read and

Write modes.

Functional Description

The CY62146CV30 is a high-performance CMOS static RAM

organized as 256K words by 16 bits. This device features ad-

vanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life™ (MoBL™) in portable

applications such as cellular telephones. The device also has

an automatic power-down feature that significantly reduces

The CY62146CV30 is available in 48-ball FBGA packaging.

Logic Block Diagram

DATA IN DRIVERS

256K × 16

RAM Array

I/O – I/O

2048 × 2048

I/O – I/O

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05203 Rev. *A

Revised April 24, 2002

12 3 4 5 6 7...12

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与CY62146CV30LL-70BVIT相关器件

型号	品牌	获取价格	描述	数据表
CY62146DV30	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146DV30_09	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146DV30L	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146DV30L-55BVI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146DV30L-55BVIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62146DV30L-55BVXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146DV30L-55ZSXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146DV30L-55ZSXIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62146DV30L-70BVI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146DV30L-70BVIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48

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