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CY62138VNLL-70BAIT PDF预览

CY62138VNLL-70BAIT

更新时间： 2024-09-15 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
8页 410K
描述
Standard SRAM, 256KX8, 70ns, CMOS, PBGA36, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-36

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CY62138VNLL-70BAIT 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：TFBGA,针数：36
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.78
最长访问时间：70 nsJESD-30 代码：S-PBGA-B36
JESD-609代码：e0长度：7 mm
内存密度：2097152 bit内存集成电路类型：STANDARD SRAM
内存宽度：8功能数量：1
端子数量：36字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX8封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装形状：SQUARE
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
宽度：7 mmBase Number Matches：1

CY62138VNLL-70BAIT 数据手册

 浏览型号CY62138VNLL-70BAIT的Datasheet PDF文件第2页浏览型号CY62138VNLL-70BAIT的Datasheet PDF文件第3页浏览型号CY62138VNLL-70BAIT的Datasheet PDF文件第4页浏览型号CY62138VNLL-70BAIT的Datasheet PDF文件第5页浏览型号CY62138VNLL-70BAIT的Datasheet PDF文件第6页浏览型号CY62138VNLL-70BAIT的Datasheet PDF文件第7页 
CY62138VN MoBL®  
256K x 8 Static RAM  
Features  
Functional Description  
• Temperature Ranges  
The CY62138VN is a high-performance CMOS static RAM  
organized as 256K words by 8 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that reduces power  
consumption by 99% when addresses are not toggling. The  
device can be put into standby mode when deselected (CS1  
HIGH or CS2 LOW). Writing to the device is accomplished by  
taking Chip Enable One (CS1) and Write Enable (WE) inputs  
LOW and Chip Enable Two (CS2) HIGH. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location  
specified on the address pins (A0 through A17).Reading from  
the device is accomplished by taking Chip Enable One (CS1)  
and Output Enable (OE) LOW while forcing Write Enable (WE)  
and Chip Enable Two (CS2) HIGH. Under these conditions, the  
contents of the memory location specified by the address pins  
will appear on the I/O pins.The eight input/output pins (I/O0  
through I/O7) are placed in a high-impedance state when the  
device is deselected (CS1 HIGH or CS2 LOW), the outputs are  
disabled (OE HIGH), or during a write operation (CS1 LOW,  
CS2 HIGH, and WE LOW).  
— Industrial: –40°C to 85°C  
• Low voltage range:  
— 2.7–3.6V  
• Ultra-low active power  
• Low standby power  
• Easy memory expansion with CS1/CS2 and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Offered in standard non-lead-free 36-ball FBGA  
package  
Logic Block Diagram  
PinConfiguration  
FBGA  
TOP View  
1
2
4
3
5
6
A8  
I/O  
A
A
A1  
A2  
CS2  
A 0  
I/O  
6
A
B
C
3
A
WE  
NC  
A7  
4
0
4
I/O  
0
Data in Drivers  
A
I/O  
I/O  
1
5
5
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
1
2
3
4
5
A
A
A
0
1
2
3
4
5
6
7
8
V
V
CC  
D
E
F
SS  
A
A
256K x 8  
ARRAY  
V
CC  
V
SS  
A
A
A
A
NC  
CS  
A
17  
I/O  
I/O  
2
6
A
G
H
I/O  
1
I/O  
OE  
A
15  
16  
7
3
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CS  
CS12  
WE  
I/O  
A
A
A
13  
A
A9  
A14  
12  
11  
10  
OE  
Product Portfolio  
Power Dissipation (Industrial)  
Operating (Icc Standby (ISB2)  
VCC Range  
)
[1]  
Product  
VCC(min) VCC(typ)  
VCC(max)  
Speed  
Typ.[1]  
Maximum  
Typ.[1]  
Maximum  
CY62138VN  
2.7V  
3.0V  
3.6V  
70 ns  
7 mA  
15 mA  
1 µA  
15 µA  
Note:  
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V Typ, T = 25°C.  
CC  
CC  
A
Cypress Semiconductor Corporation  
Document #: 001-06513 Rev. **  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 2, 2006  
[+] Feedback  
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