Datasheet > CY62146CV18

CY62146CV18

更新时间： 2024-09-15 04:53:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	294K
描述
256K x 16 Static RAM

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中文翻译

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数据手册

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CY62146CV18 数据手册

CY62146CV18 MoBL2™

256K x 16 Static RAM

reduces power consumption by 99% when addresses are not

toggling. The device can also be put into standby mode when

deselected (CE HIGH). The input/output pins (I/O₀through

I/O₁₅) are placed in a high-impedance state when deselected

(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

Features

• High Speed

— 55 ns and 70 ns availability

• Low voltage range:

— 1.65V–1.95V

• Pin Compatible with CY62146BV18

• Ultra-low active power

— Typical Active Current: 0.5 mA @ f = 1 MHz

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₆). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₇).

— Typical Active Current: 2 mA @ f = f_max(70 ns speed)

• Low standby power

• Easy memory expansion with CE and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

Functional Description

The CY62146CV18 is a high-performance CMOS static RAM

organized as 256K words by 16 bits. These devices feature

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL™) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

The CY62146CV18 is available in a 48-Ball FBGA package.

Logic Block Diagram

DATA IN DRIVERS

256K x 16

RAM Array

I/O –I/O

2048 x 2048

I/O –I/O

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05010 Rev. *C

Revised August 28, 2002

12 3 4 5 6 7...12

中文翻译

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与CY62146CV18相关器件

型号	品牌	获取价格	描述	数据表
CY62146CV18LL-55BAI	CYPRESS	获取价格	Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
CY62146CV18LL-55BAI	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 55ns, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
CY62146CV18LL-55BAIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
CY62146CV18LL-55BVIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CY62146CV18LL-70BAI	CYPRESS	获取价格	Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
CY62146CV18LL-70BVI	CYPRESS	获取价格	Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CY62146CV18LL-70BVIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CY62146CV30	CYPRESS	获取价格	256K x 16 Static RAM
CY62146CV30LL-55BAI	CYPRESS	获取价格	256K x 16 Static RAM
CY62146CV30LL-55BAIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FINE PITCH, TBGA-

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