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CY62138VL-70ZI PDF预览

CY62138VL-70ZI

更新时间: 2024-09-15 15:44:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
9页 241K
描述
Standard SRAM, 256KX8, 70ns, CMOS, PBGA48, 7 X 7 MM, MINI, FBGA-48

CY62138VL-70ZI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:7 X 7 MM, MINI, FBGA-48针数:48
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.85
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:S-PBGA-B48JESD-609代码:e0
内存密度:2097152 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:48
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA36,6X8,30
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:1.8/3.3 V认证状态:Not Qualified
最大待机电流:0.000001 A最小待机电流:1 V
子类别:SRAMs最大压摆率:0.015 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30Base Number Matches:1

CY62138VL-70ZI 数据手册

 浏览型号CY62138VL-70ZI的Datasheet PDF文件第2页浏览型号CY62138VL-70ZI的Datasheet PDF文件第3页浏览型号CY62138VL-70ZI的Datasheet PDF文件第4页浏览型号CY62138VL-70ZI的Datasheet PDF文件第5页浏览型号CY62138VL-70ZI的Datasheet PDF文件第6页浏览型号CY62138VL-70ZI的Datasheet PDF文件第7页 
PRELIMINARY  
CY62138V MoBL™  
256K x 8 Static RAM  
Writing to the device is accomplished by taking chip enable  
Features  
one (CS ) and write enable (WE) inputs LOW and chip enable  
1
• Low voltage range:  
two (CS ) input HIGH. Data on the eight I/O pins (I/O through  
2
0
I/O ) is then written into the location specified on the address  
7
— 1.8 3.3V  
pins (A through A ).  
0
17  
• Ultra-low active power  
• Low standby power  
• Easy memory expansion with CS /CS and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Reading from the device is accomplished by taking chip en-  
able one (CS ) and output enable (OE) LOW while forcing  
1
1
2
write enable (WE) and chip enable two (CS ) HIGH. Under  
2
these conditions, the contents of the memory location speci-  
fied by the address pins will appear on the I/O pins.  
The eight input/output pins (I/O through I/O ) are placed in a  
0
7
high-impedance state when the device is deselected (CS  
HIGH or CS2 LOW), the outputs are disabled (OE HIGH), or  
1
Functional Description  
during a write operation (CS LOW, CS HIGH, and WE LOW).  
1
2
The CY62138V is a high-performance CMOS static RAM or-  
ganized as 262,144 words by 8 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life (MoBL™) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
power consumption by 99% when addresses are not toggling.  
The device can be put into standby mode when deselected  
The 62138V MoBL SRAM has an extremely wide operating  
voltage range. The datasheet has been specified to accurately  
describe the device behavior at three common voltage ranges  
(3.32.7, 2.72.3, 2.31.8)  
The CY62138V is available in a 36-ball FBGA.  
(CS HIGH or CS LOW).  
1
2
Logic Block Diagram  
Pin Configuration  
FBGA  
TOP View  
1
2
4
3
5
6
A8  
I/O  
A
A
A1  
A2  
CS2  
A 0  
I/O  
6
A
B
C
3
I/O  
0
Data in Drivers  
A
WE  
NC  
A7  
4
0
4
I/O  
I/O  
I/O  
I/O  
I/O  
1
2
3
4
5
A
A
A
0
1
2
3
4
5
6
A
I/O  
I/O  
1
5
5
A
A
A
A
V
V
256K x 8  
ARRAY  
D
E
F
CC  
SS  
A
7
8
V
CC  
V
SS  
A
NC  
CS  
A
I/O  
I/O  
2
17  
6
I/O  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CS  
1
2
CS  
A
G
H
I/O  
1
I/O  
4
OE  
A
15  
I/O  
16  
7
WE  
62138V-1  
OE  
A
A
A
13  
A
A14  
A9  
12  
11  
10  
62138V–2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
September 1998  

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