Datasheet > 暂无类别数据> CY62138FV30LL-45ZAXAT

CY62138FV30LL-45ZAXAT

更新时间： 2024-11-05 13:07:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	642K
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CY62138FV30 MoBL^®

2-Mbit (256K x 8) Static RAM

Features

Functional Description

■ Very High-speed: 45 ns

The CY62138FV30^[1]is a high performance CMOS static RAM

organized as 256K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption. Place the device into standby mode reducing

power consumption when deselected (CE₁HIGH or CE₂LOW).

■ Temperature ranges

❐ Industrial: –40 °C to 85 °C

❐ Automotive-A: –40 °C to 85 °C

■ Wide voltage range: 2.20 V to 3.60 V

■ Pin compatible with CY62138CV25/30/33

To write to the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location specified

on the address pins (A₀through A₁₇).

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 5 A

■ Ultra low active power

❐ Typical active current: 1.6 mA at f = 1 MHz

To read from the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ Easy memory expansion with CE₁, CE₂, and OE Features

■ Automatic power down when deselected

The eight input and output pins (I/O₀through I/O₇) are placed in

a high impedance state when the device is deselected (CE₁

HIGH or CE₂LOW), the outputs are disabled (OE HIGH), or

during a write operation (CE₁LOW and CE₂HIGH and WE

LOW).

■ complementary metal oxide semiconductor (CMOS) for

Optimum speed and power

■ Offered in Pb-free 36-Ball VFBGA, 32-Pin TSOP II, 32-Pin

SOIC, 32-Pin TSOP I and 32-Pin STSOP Packages

Logic Block Diagram

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 001-08029 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 4, 2010

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CY62138FV30LL-45ZAXAT 替代型号

型号	品牌	替代类型	描述	数据表
CY62138FV30LL-45ZAXA	CYPRESS	完全替代	2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45ZAXI	CYPRESS	完全替代	2-Mbit (256K x 8) Static RAM

与CY62138FV30LL-45ZAXAT相关器件

型号	品牌	获取价格	描述	数据表
CY62138FV30LL-45ZAXI	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45ZAXI	INFINEON	获取价格	Asynchronous SRAM
CY62138FV30LL-45ZAXIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, 1.20 MM HEIGHT, LEAD FREE, STSOP-
CY62138FV30LL-45ZAXIT	INFINEON	获取价格	Asynchronous SRAM
CY62138FV30LL-45ZSXI	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45ZXI	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45ZXI	INFINEON	获取价格	Asynchronous SRAM
CY62138FV30LL-45ZXIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 20 MM, 1 MM HEIGHT, LEAD FREE, TSOP1-32
CY62138FV30LL-45ZXIT	INFINEON	获取价格	Asynchronous SRAM
CY62138V	CYPRESS	获取价格	256K x 8 Static RAM

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