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CY62138V_06

更新时间： 2024-09-15 04:53:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 320K
描述
2-Mbit (256K x 8) Static RAM

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中文翻译

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CY62138V_06 数据手册

 浏览型号CY62138V_06的Datasheet PDF文件第2页浏览型号CY62138V_06的Datasheet PDF文件第3页浏览型号CY62138V_06的Datasheet PDF文件第4页浏览型号CY62138V_06的Datasheet PDF文件第5页浏览型号CY62138V_06的Datasheet PDF文件第6页浏览型号CY62138V_06的Datasheet PDF文件第7页 
CY62138V MoBL™  
2-Mbit (256K x 8) Static RAM  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that reduces power  
consumption by 99% when addresses are not toggling. The  
device can be put into standby mode when deselected (CS1  
HIGH or CS2 LOW).  
Features  
• High Speed:  
— 70 ns  
• Low voltage range:  
— 2.7V – 3.6V  
Writing to the device is accomplished by taking Chip Enable  
One (CS1) and Write Enable (WE) inputs LOW and Chip  
Enable Two (CS2) HIGH. Data on the eight I/O pins (I/O0  
through I/O7) is then written into the location specified on the  
address pins (A0 through A17).  
• Ultra-low active power  
• Low standby power  
• Easy memory expansion with CS1/CS2 and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Available in non Pb-free 36-ball FBGA package  
Reading from the device is accomplished by taking Chip  
Enable One (CS1) and Output Enable (OE) LOW while forcing  
Write Enable (WE) and Chip Enable Two (CS2) HIGH. Under  
these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CS1  
HIGH or CS2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CS1 LOW, CS2 HIGH, and WE LOW).  
Functional Description  
The CY62138V is a high-performance CMOS static RAM  
organized as 256K words by 8 bits. This device features  
advanced circuit design to provide ultra-low active current.  
The CY62138V is available in a 36-ball FBGA package.  
Logic Block Diagram  
Pin Configuration  
36-ball FBGA  
TOP View  
1
2
4
3
5
6
A8  
I/O  
A
A
A1  
A2  
CS2  
A 0  
I/O  
6
A
B
C
3
A
WE  
NC  
A7  
4
0
4
I/O  
0
Data in Drivers  
A
I/O  
I/O  
1
5
5
I/O  
1
A
A
A
0
1
2
3
4
5
6
7
8
I/O  
V
V
2
CC  
D
E
F
SS  
A
A
256K x 8  
ARRAY  
I/O  
3
A
A
V
CC  
V
SS  
I/O  
4
A
A
NC  
CS  
A
17  
I/O  
I/O  
2
6
I/O  
5
A
G
H
I/O  
1
I/O  
OE  
A
I/O  
3
16  
15  
7
6
POWER  
DOWN  
COLUMN  
DECODER  
CS  
CS12  
WE  
I/O  
7
A
12  
A
A
13  
A
A9  
A14  
11  
10  
OE  
Cypress Semiconductor Corporation  
Document #: 38-05088 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 21, 2006  
[+] Feedback  
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