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CY62138FV30LL-45BVXI PDF预览

CY62138FV30LL-45BVXI

更新时间： 2024-11-05 02:52:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 1006K
描述
2-Mbit (256K x 8) Static RAM

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CY62138FV30LL-45BVXI 数据手册

 浏览型号CY62138FV30LL-45BVXI的Datasheet PDF文件第2页浏览型号CY62138FV30LL-45BVXI的Datasheet PDF文件第3页浏览型号CY62138FV30LL-45BVXI的Datasheet PDF文件第4页浏览型号CY62138FV30LL-45BVXI的Datasheet PDF文件第5页浏览型号CY62138FV30LL-45BVXI的Datasheet PDF文件第6页浏览型号CY62138FV30LL-45BVXI的Datasheet PDF文件第7页 
CY62138FV30 MoBL®  
2-Mbit (256K x 8) Static RAM  
Features  
Functional Description [1]  
• Very high speed: 45 ns  
The CY62138FV30 is a high performance CMOS static RAM  
organized as 256K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption. Place the device into standby  
mode reducing power consumption when deselected (CE1  
HIGH or CE2 LOW).  
• Wide voltage range: 2.20V–3.60V  
• Pin compatible with CY62138CV25/30/33  
• Ultra low standby power  
— Typical standby current: 1 µA  
— Maximum standby current: 5 µA  
• Ultra low active power  
— Typical active current: 1.6 mA @ f = 1 MHz  
• Easy memory expansion with CE1, CE2, and OE features  
• Automatic power down when deselected  
• CMOS for optimum speed and power  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. Data on the eight  
IO pins (IO0 through IO7) is then written into the location  
specified on the address pins (A0 through A17).  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins appear on  
the IO pins.  
• Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin  
SOIC, 32-pin TSOP I and 32-pin STSOP packages  
The eight input and output pins (IO0 through IO7) are placed  
in a high impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW and CE2 HIGH and WE  
LOW).  
Logic Block Diagram  
IO  
0
DATA IN DRIVERS  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
1
IO  
2
256K x 8  
ARRAY  
IO  
3
IO  
IO  
IO  
IO  
4
5
6
7
A
A
A
9
10  
11  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-08029 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 26, 2007  
[+] Feedback  
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与CY62138FV30LL-45BVXI相关器件

型号 品牌 获取价格 描述 数据表
CY62138FV30LL-45BVXIT INFINEON

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 		Asynchronous SRAM
CY62138FV30LL-45SXI CYPRESS

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 		2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45SXIT CYPRESS

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 		Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62138FV30LL-45ZAXA CYPRESS

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 		2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45ZAXA INFINEON

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 		Asynchronous SRAM
CY62138FV30LL-45ZAXAT CYPRESS

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 		暂无描述
CY62138FV30LL-45ZAXAT INFINEON

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 		Asynchronous SRAM
CY62138FV30LL-45ZAXI CYPRESS

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 		2-Mbit (256K x 8) Static RAM
CY62138FV30LL-45ZAXI INFINEON

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 		Asynchronous SRAM
CY62138FV30LL-45ZAXIT CYPRESS

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 		Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, 1.20 MM HEIGHT, LEAD FREE, STSOP-

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