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CY2LL842ZCT PDF预览

CY2LL842ZCT

更新时间: 2024-11-20 14:33:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
14页 159K
描述
Line Transceiver, 2 Func, 2 Driver, 2 Rcvr, PDSO16, 4.40 MM, TSSOP-16

CY2LL842ZCT 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, TSSOP-16
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92Is Samacsys:N
差分输出:YES驱动器位数:2
输入特性:DIFFERENTIAL接口集成电路类型:LINE TRANSCEIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
功能数量:2端子数量:16
最高工作温度:70 °C最低工作温度:
最小输出摆幅:0.247 V封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified最大接收延迟:6 ns
接收器位数:2座面最大高度:1.1 mm
子类别:Line Driver or Receivers最大压摆率:25 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
最大传输延迟:6 ns宽度:4.4 mm
Base Number Matches:1

CY2LL842ZCT 数据手册

 浏览型号CY2LL842ZCT的Datasheet PDF文件第2页浏览型号CY2LL842ZCT的Datasheet PDF文件第3页浏览型号CY2LL842ZCT的Datasheet PDF文件第4页浏览型号CY2LL842ZCT的Datasheet PDF文件第5页浏览型号CY2LL842ZCT的Datasheet PDF文件第6页浏览型号CY2LL842ZCT的Datasheet PDF文件第7页 
ComLink™ Series  
CY2LL842  
Two-channel LVDS Repeater/Mux  
Features  
Description  
ANSI TIA/EIA-644-1995-compliant  
Does not exceed Belcore 802.3 standards  
Operation at => 350 MHz700 Mbps  
Single 2 × 2  
Low-voltage differential signaling (LVDS) with output  
voltages of ± 350 mV into 100-ohm load version (Std)  
Single 3.3V supply  
Accepts ± 350 mV differential inputs  
Output drivers are high-impedance when disabled or  
when VDD 1.5V  
16-pin SOIC/TSSOP packages  
Industrial version available  
The CYPRESS CY2LL842 are differential line drivers and  
receivers that utilize LVDS to achieve signaling rates of 650  
Mbs. The receiver outputs can be switched to either or both  
drivers thru the multiplexer control signals S0/S1. This  
provides flexibility in application for either a splitter or router  
configuration with a single device.  
The CYPRESS CY2LL842 is configured as  
two-channel repeater/Mux.  
a single  
The LVDS standard provides a minimum differential output  
voltage of 247 mV into a 100-ohm load and receipt of as little  
as 100-mV signals with up to 1V of DC offset between trans-  
mitter and receiver.  
A doubly terminated bus LVDS line enables multipoint config-  
urations.  
Designed for both point to point based-band multi-point data  
transmission over controlled impedance lines.  
Block Diagram  
Pin Configuration  
VDD  
1B  
1A  
S0  
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
VDD  
1DE  
VDD  
1Y  
1A  
1B  
1Y  
1Z  
1Z  
1DE  
S1  
2DE  
2Z  
2A  
2B  
2A  
2Y  
2Z  
2Y  
2B  
GND  
GND  
GND  
2DE  
S0 S1  
16 pin SOIC/TSSOP  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07063 Rev. **  
Revised July 29, 2002  

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