Datasheet > CY2PP318

CY2PP318

更新时间： 2024-11-19 23:44:59

品牌	Logo	应用领域
其他 - ETC		时钟
页数	文件大小	规格书
12页	196K
描述
Clocks and Buffers

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数据手册

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CY2PP318 数据手册

FastEdge™ Series

CY2PP318

PRELIMINARY

1 of 2:8 Differential Fanout Buffer

Features

Description

The CY2PP318 is a low-skew, low propagation delay 1-to-8

differential fanout buffer targeted to meet the requirements of

high-performance clock and data distribution applications. The

device is implemented on SiGe technology and has a fully

differential internal architecture that is optimized to achieve

low signal skews at operating frequencies of up to 1.5 GHz.

• Eight ECL/PECL differential outputs

• Two ECL/PECL differential inputs

• Hot-swappable/-insertable

• 50-ps output-to-output skew

• < 500-ps device-to-device skew

• Less than 10 ps intrinsic jitter

• 500-ps propagation delay (typical)

• Operation up to 1.5 GHz

• PECL mode supply range: V_CC= 2.375V to 3.465V with

V_EE= 0V

• ECL mode supply range: V_{E E}= –2.375V to –3.465V with

V_CC= 0V

The device features two differential input paths that are multi-

plexed internally. This mux is controlled by the CLK_SEL pin.

The CY2PP318 may function not only as a differential clock

buffer but also as a signal-level translator and fanout on

ECL/PECL signal to eight ECL/PECL differential loads. An ex-

ternal bias pin, VBB, is provided for this purpose. In such an

application, the VBB pin should be connected to either one of

the CLKA# or CLKB# inputs and bypassed to ground via a

0.01-µF capacitor.

Since the CY2PP318 introduces negligible jitter to the timing

budget, it is the ideal choice for distributing high frequency,

high precision clocks across back-planes and boards in

communication systems. Furthermore, advanced circuit

design schemes, such as internal temperature compensation,

ensure that the CY2PP318 delivers consistent, guaranteed

performance over different platforms.

• Industrial temperature range: –40°C to 85°C

• 28-pin PLCC package

• Temperature compensation as 100K ECL

Pin Configuration

Block Diagram

Q0#

Q1#

VCCO

Q2#

CLKA

Q 0

C L K B #

N C

CLKA#

Q 0 #

Q 1

Q 7 #

Q3#

V C C O

VEE

V C C O

VCCO

Q 1 #

Q 7

Q 6 #

Q 6

Q 2

Q4#

CLKB

Q 2 #

CLKB#

Q5#

VEE

CLK_SEL

Q6#

VEE

Q7#

VBB

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07501 Rev.*B

Revised February 8, 2004

12 3 4 5 6 7...12

中文翻译

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与CY2PP318相关器件

型号	品牌	获取价格	描述	数据表
CY2PP318JIT	CYPRESS	获取价格	Low Skew Clock Driver, 2PP Series, 8 True Output(s), 0 Inverted Output(s), PQCC28, PLASTIC
CY2PP3210	CYPRESS	获取价格	Dual 1:5 Differential Clock / Data Fanout Buffer
CY2PP3210AI	CYPRESS	获取价格	Dual 1:5 Differential Clock / Data Fanout Buffer
CY2PP3210AIT	CYPRESS	获取价格	Dual 1:5 Differential Clock / Data Fanout Buffer
CY2PP3220	CYPRESS	获取价格	Dual 1:10 Differential Clock / Data Fanout Buffer
CY2PP3220AI	CYPRESS	获取价格	Dual 1:10 Differential Clock / Data Fanout Buffer
CY2PP3220AIT	CYPRESS	获取价格	Dual 1:10 Differential Clock / Data Fanout Buffer
CY2PP326	CYPRESS	获取价格	2 x 2 Clock and Data Switch Buffer
CY2PP326AI	CYPRESS	获取价格	2 x 2 Clock and Data Switch Buffer
CY2PP326AIT	CYPRESS	获取价格	2 x 2 Clock and Data Switch Buffer

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